臺灣博碩士論文加值系統

本論文主要在探討奈米線電晶體之製備。以介電泳法來排列奈米線，因為這項技術不需要特殊設備、低成本、方便。但是在排列奈米線後，存在著奈米線與電極接觸電阻過高的問題。為了改善利接觸電阻過高的問題，本論文開發出熱壓法及自我對準技術來改善接觸電阻問題，並製作元件探討其電性。熱壓法是利用鍍有類鑽碳膜的矽基板為壓版，在180oC下將奈米線壓入電極中。由電性圖可知，兩端電阻在經過熱壓後已大幅降低。利用此法改變不同電極厚度，所製備的電晶體電性其threshold voltage介於-7.4~2.8V 、electron mobility介於5.6~41.7cm2V-1s-1、on-off current ratio 介於104~106。而自我對準技術則是利用從透明基板背面曝光之方式，以第一層金屬電極為光罩，將第二層電極準確地沉積在第一層電極上。在沉積上電極後可大幅地將低接觸電阻，也解決了一般以光微影定義第二層圖案需對準的問題。以PVP為介電層，利用此法所製備的電晶體特性為on/off current ratio~104，subthreshold slope~840 mV/dec，electron mobility~86.5 cm2V-1s-1，threshold voltage~4.6 V。

The main subject of this dissertation was about the fabrication of nanowire field-effect transistors (NW-FETs). In this study, dielectrophoresis (DEP) was applied to manipulate nanowires because it’s easy, low cost and doesn’t require specialized skills and equipment. But the poor contact between nanowires and electrodes after DEP is the problem for fabricating NW-FETs. In order to overcome the problem, hot-pressing method and self-aligned technique were applied to lower the contact resistance. Hot-pressing method was using a piece of Si substrate coated with DLC (diamond-like carbon) to cover the sample substrate and applied a constant force under high temperature. After hot-pressing process, nanowires were sunk into electrodes and I-V curve shows contact resistance was improved significantly. The high-performance NW-FETs showed threshold voltage of -7.4~2.8V, electron mobility of 5.6~41.7cm2V-1s-1, on-off current ratio of 104~106. About the self-aligned method, the second metal layer pattern was defined using first metal layer as mask during the backside exposure. By I-V characteristics, the high performance NW-FETS showed on/off current ratio of 104,subthreshold slope of 840mV/dec, electron mobility of 86.5cm2V-1s-1, threshold voltage of 4.6V. The high performance device fabricated by our methods indicated DEP combined with hot-pressed method or self-aligned technique were with the potential to be applied to the fabrication of flexible electronics in large-area.

摘要 I
ABSTRACT II
誌謝 III
目錄 V
表目錄 IX
圖目錄 X
第一章 緒論 1
1-1 前言 1
1-2 奈米科技之發展 3
1-2-1 奈米材料 3
1-2-2 奈米元件製作瓶頸 4
1-2-3 奈米線的應用 6
1-3 全球奈米科技研發趨勢 7
1-4 研究動機 8
第二章 理論基礎與文獻回顧 12
2-1 電晶體簡介(Transistor) 12
2-2 FET工作原理與理論計算 14
2-2-1兩端特性 14
2-2-2三端特性 14
2-2-3 載子遷移率(Carrier Mobility) 15
2-2-4 臨界電壓(Threshold voltage, Vth) 17
2-2-5 轉移電導值(Transconductance, gm) 17
2-2-6 開關電流比(On/Off current ratio) 18
2-2-7 次臨界擺幅(Substhreshold swing, S) 18
2-3 奈米線電晶體研究近況 19
2-3-1多通道奈米線電晶體(multi-channel NWFETs) 21
2-3-2 三維奈米線電晶體(Three-dimensional NWFETs) 23
2-3-3 核/殼奈米線電晶體(core/shell NWFETs) 24
2-3-4 環繞式閘極奈米線電晶體(surrounding-gate NWFETs) 25
2-4 奈米線的組裝 27
2-4-1 間接組裝 27
2-4-2 直接組裝 30
第三章 實驗方法與步驟 52
3-1實驗流程 52
3-2實驗設備 53
3-2-1單面光罩對準機(Single-side Mask aligner) 53
3-2-2電子束蒸鍍機(Electron-Beam Evaporator) 53
3-2-3函數波形產生器(Function Generator) 54
3-2-4 示波器(Oscilloscope) 54
3-2-5 壓印機(Hot Imprinter) 55
3-3實驗材料 56
3-3-1 基板材料 56
3-3-2 有機材料 56
3-3-2 無機材料 57
3-3-3 金屬材料 57
3-3-4 基板清洗溶劑及實驗氣體 58
3-4實驗步驟 59
3-4-1 結合介電泳法與熱壓法製備氧化鋅奈米線電晶體 59
3-4-2 結合介電泳法與自我對準技術於透明基板製作奈米線電晶體 61
3-5實驗鑑定 64
3-5-1 掃描式電子顯微鏡 64
3-5-2 表面輪廓儀(Alpha-Step IQ) 65
3-5-3半導體電性量測系統 65
第四章 結果與討論 70
4-1 結合介電泳法與熱壓法製備氧化鋅奈米線電晶體 70
4-1-1 以電極厚度為100 nm進行熱壓法製作奈米線電晶體 71
4-1-2 以電極厚度為380 nm進行熱壓法製作奈米線電晶體 73
4-1-3 小結 76
4-2 結合介電泳法與自我對準技術於透明基板製作奈米線電晶體 77
4-2-1 以光阻直接作為介電層之電晶體製作 77
4-2-2 披覆PVP為介電層之電晶體製作 80
4-2-3 小結 82
第五章 結論 100
參考文獻 102

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