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研究生:張瑞廷
研究生(外文):Jui-Ting Chang
論文名稱:CMOS/MEMS射頻功率放大器與四次諧波混頻器之研製
論文名稱(外文):Design and Implementation of a CMOS/MEMS RF Power Amplifier and a Quadruple Sub-harmonic Mixer
指導教授:王永和王永和引用關係陳家豪陳家豪引用關係
指導教授(外文):Yeong-Her WangJa-Hao Chen
學位類別:碩士
校院名稱:國立成功大學
系所名稱:微電子工程研究所碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:73
中文關鍵詞:CMOS-MEMS功率分配器(合成器)功率放大器四次諧波混頻器雙工濾波器集總元件
外文關鍵詞:CMOS-MEMSLumped elementsFrequency diplexerQuadruple Sub-harmonic MixerPower AmplifierPower divider (combiner)
相關次數:
  • 被引用被引用:6
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本論文首先探討應用於802.11a頻段之5.8-GHz CMOS功率放大器。利用TSMC 0.18μm 1P6M CMOS製程並搭配國家晶片中心(CIC)所使用之MEMS後製程,製作出Lumped型式之Wilkinson 功率分配器,由於MEMS後製程與一般CMOS製程相比,其可製作出高Q值的電感,使得所設計之MEMS功率分配器
於5.8-GHz頻段時,能有較低之插入損耗(3.72-dB)。再藉由所設計之功率分配器結合兩個5.8-GHz頻段之CMOS功率放大器,將可提升功率放大器的輸出功率,
模擬結果得到增益為10.7-dB與輸出P1dB為22.6-dBm。
本文主要提供一個新式的四次諧波混頻器,利用P15 pHEMT GaAs製程來實現一個晶片面積為0.82 × 0.7 mm2的混頻器。這個新式的四次諧波混頻器結合集總式雙工濾波器將RF與LO訊號結合輸入至APDP二極體,並且經由低通濾波器混出IF訊號。此雙工濾波器的低頻通帶提供LO訊號輸入,高頻通帶提供RF訊號輸入,如此LO與RF訊號將會有良好的隔離度,並且獲得一寬頻的頻率響應,而低通濾波器濾波範圍為DC到2.5GHz頻段。此設計之四次諧波混頻器量測的轉換損耗為12.5-16.5 dB,LO-RF的隔離度超過15 dB,而且在16-31 GHz RF頻段的4LO-RF隔離度為50-59 dB,而輸入1dB壓縮點為2dBm。
A 5.8-GHz high-linearity CMOS power amplifier using a Wilkinson power combiner, implemented through a 0.18 μm RF CMOS/MEMS technology is investigated. The key issue is the use of an inductor to deliver the high quality factor (Q) which can improve the poor RF performances of the traditional inductor due to the thin metallization and substrate related losses. The proposed power divider achieved a lower insertion loss of 3.72-dB at 5.8-GHz. By combining two 5.8-GHz CMOS power amplifiers with the proposed divider, the proposed circuit delivers an output P1dB of 22.6-dBm with a power gain of 10.7-dB. The chip area is 1.4 × 1 mm2.

The second part of this thesis presents that a novel 16-31 GHz quadruple sub-harmonic monolithic passive mixer with a chip dimension of 0.82 × 0.7 mm2 is designed and fabricated using the 0.15 µm GaAs pHEMT process. The novel configuration of the quadruple sub-harmonic mixer consists of a lumped frequency diplexer and a low-pass filter utilizing a pair of anti-parallel Schottky barrier diode to achieve quadruple sub-harmonic mixing mechanism. The lumped frequency diplexer formed with a low-pass network and a high-pass network is used to reduce the chip dimension while operating at low frequency band and to improve the isolation between the RF and LO ports with a broadband operation. The low-pass filter supports an IF frequency range from DC to 2.5 GHz. From the measured results, the mixer exhibits a 12.5-16.5 dB conversion loss, a LO-to-RF isolation better than 15 dB, a 50-59 dB high 4LO-to-RF isolation over 16-31 GHz RF bandwidth, and an input 1 dB compression power of 2 dBm.
第一章 緒論 1
1.1 研究背景 1
1.2 論文綱要 2
第二章 微波收發機架構簡介 3
2.1 收發機簡介 3
2.1.1 超外差式接收機 4
2.1.2 直接降頻式接收機 5
2.1.3 直接升頻式發射機 (direct conversion transmitter) 8
2.1.4 二次升頻式發射機 (Two Step transmitter ) 9
2.2 功率放大器簡介 10
2.2.1 偏壓點的選擇 10
2.2.2 負載線理論(Load Line Theory)求輸出功率等位線[7] 13
2.2.3 負載調整法 15
2.3.1 二極體混頻器 (Diode Mixer)[9] 16
2.3.2 電阻式混頻器 (Resistive FET Mixer) 19
2.4 微波電路基本參數 21
2.4.1 轉換增益/損耗(Conversion Gain/Loss) 21
2.4.2 隔離度(Isolation) 22
2.4.3 1dB增益壓縮點(1dB compression point;P1dB) 23
2.4.4 三階截斷點(Third order intercept point;IP3) 24
2.4.5 雜訊指數(Noise Figure;NF) 26
第三章 5.8GHz CMOS MEMS功率結合之功率放大器 28
3.1 研究動機 28
3.2 電路架構與設計原理 29
3.2.1 功率放大器相關理論 30
3.2.2 利用微機電技術之Wilkinson功率分配器(合成器) 33
3.2.3 CMOS功率放大器電路架構 36
3.2.4 設計流程圖 40
3.3 模擬結果 41
3.4 電路佈局 42
3.4.1 利用微機電技術之Wilkinson功率分配器電路佈局 42
3.4.2 5.8GHz CMOS-MEMS 功率結合之功率放大器電路佈局 43
3.5 晶片測試 45
3.5.1 利用微機電技術之Wilkinson功率分配器晶片測試 45
3.5.2 5.8GHz CMOS MEMS功率結合之功率放大器測試 47
3.6 結果討論 49
第四章 微小化16-31GHz PHEMT四次諧波混頻器 51
4.1研究動機 51
4.2 電路架構與設計原理 52
4.2.1 反向二極體對次諧波混頻器[30] 54
4.2.2 雙工濾波器(Frequency Diplexer) 57
4.2.3 設計流程圖 59
4.3 模擬結果 60
4.4 電路佈局 63
4.5 晶片測試 64
4.6 結果討論 67
第五章 69
結論 69
參考文獻 70

表1- 1 IEEE商業微波頻帶稱號 2
表2- 1 功率放大器的分類 11
表2- 2 A類、B類之Idc、I1與效率比較 12
表2- 3 混頻器輸出成份 18
表3- 1 Wilkinson Power divider CMOS與MEMS製程比較 35
表3- 2 CMOS兩級功率放大器模擬規格表 39
表3- 3 CMOS-MEMS功率結合之功率放大器預計規格表 41
表3- 4 MEMS Wilkinson Power divider預計規格與實測比較表 49
表3- 5 Wilkinson power divider文獻比較表 49
表3- 6 CMOS-MEMS功率結合之功率放大器預計規格與實測比較表 50
表4- 1 寬頻四次諧波混頻器預計規格表 63
表4- 2 寬頻四次諧波混頻器預計規格表 68
表4- 3 次諧波混頻器文獻比較表 69

圖2- 1 收發機架構圖 (a)發射模組 (b)接收模組 3
圖2- 2 二次降頻超外差式接收機架構 4
圖2- 3 鏡像頻率訊號的干擾 5
圖2- 4 直接降頻式接收機 5
圖2- 5 DC Offset 示意圖 6
圖2- 6 二階失真效應 7
圖2- 7 直接升頻式發射機 8
圖2- 8 二階升頻式發射機 9
圖2- 9 功率放大器輸入電壓與輸出電流波形 10
圖2- 10 各類偏壓電流之傅立葉分析 12
圖2- 11 電晶體I-V curve 及負載線示意圖 13
圖2- 12 不同負載阻抗之下的負載線圖 14
圖2- 13 ADS負載模擬調整電路 15
圖2- 14 等功率圓以及等PAE圓之模擬結果 15
圖2- 15 蕭基二極體I-V特性曲線 16
圖2- 16 Diode Mixer 示意圖 19
圖2- 17 電阻式混頻器 19
圖2- 18 1dB增益壓縮點與動態範圍 23
圖2- 19 非線性系統的三階交互調變 24
圖2- 20 交互調變衍生輸出 24
圖2- 21 三階截斷點 25
圖2- 22 二級串接雙埠網路 26
圖3- 1 CMOS兩級功率放大器 29
圖3- 2 CMOS-MEMS功率結合之功率放大器 30
圖3- 3 S參數雙埠網路 30
圖3- 4 雙埠網路功率增益圖 31
圖3- 5 Wilkinson power divider 集總電路 33
圖3- 6 CMOS與MEMS製程 Insertion Loss S21、S31比較 34
圖3- 7 CMOS與MEMS製程 Return Loss S11、S22、S33比較 34
圖3- 8 CMOS與MEMS製程Isolation S23、S32比較 35
圖3- 9 CMOS兩級功率放大器電路架構圖 37
圖3- 10 CMOS兩級功率放大器返回損耗&功率增益模擬 38
圖3- 11 CMOS兩級功率放大器 Stability Factor 模擬 38
圖3- 12 CMOS兩級功率放大器 Pout, Gain, PAE 模擬 39
圖3- 13 功率放大器設計流程圖 40
圖3- 14 CMOS-MEMS功率結合之功率放大器Pout, Gain, PAE 模擬 41
圖3- 15 利用微機電技術之Wilkinson功率分配器電路佈局圖 42
圖3- 16 利用微機電技術之Wilkinson功率分配器晶片上視圖 43
圖3- 17 CMOS-MEMS功率結合之功率放大器電路佈局圖 43
圖3- 18 CMOS-MEMS功率結合之功率放大器晶片上視圖 44
圖3- 19 CMOS-MEMS功率結合之功率放大器晶片打線圖 44
圖3- 20 Wilkinson power divider Insertion Loss S21,S31量測 45
圖3- 21 Wilkinson power divider Return Loss S11, S22, S33量測 46
圖3- 22 Wilkinson power divider Isolation S23, S32量測 46
圖3- 23 5.8 GHz CMOS/MEMS power amplifier Return Loss 量測 47
圖3- 24 5.8 GHz CMOS/MEMS power amplifier Pout & Gain 量測 48
圖4- 1 傳統次諧波混頻器架構圖 53
圖4- 2 新式4次諧波混頻器電路架構圖 53
圖4- 3 二極體混頻器 (a)Single diode mixer (b)APDP mixer 56
圖4- 4 雙工濾波器電路(Frequency Diplexer)架構圖 58
圖4- 5 雙工濾波器之Insertion loss S21、S31與Isolation S23 59
圖4- 6 混頻器設計流程圖 60
圖4- 7 Conversion loss 對RF頻率模擬圖 61
圖4- 8 Conversion Loss 對LO power模擬圖 62
圖4- 9 各埠之間的Isolation模擬圖 62
圖4- 10 4倍LO頻率下的Isolation模擬圖 63
圖4- 11 寬頻16-31GHz PHEMT四次諧波混頻器電路佈局圖 64
圖4- 12 寬頻16-31GHz PHEMT四次諧波混頻器晶片上視圖 64
圖4- 13 Conversion Loss 對RF頻率模擬與量測 66
圖4- 14 Conversion loss 對LO power (18&26 GHz)量測 66
圖4- 15 Port-to-Port Isolation 模擬與量測 67
圖4- 16 Return Loss 量測 67
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