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研究生:陳昱翰
研究生(外文):Yu-Han Chen
論文名稱:原子層沉積閘極堆疊先進金氧半場效電晶體之缺陷分佈與偏壓溫度不穩定性探討
論文名稱(外文):Trap Profile and Bias Temperature Instability of ALD-HfSiON Gate Stacks in Advanced MOSFETs
指導教授:王水進
指導教授(外文):Shui-Jinn Wang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:微電子工程研究所碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:67
外文關鍵詞:HfSiONhigh-kcharge pumpinglow frequencyBTI
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隨著元件尺寸不斷的微縮,高介電係數材料(High-k material)勢必將取代傳統二氧化矽作為先進半導體製程中元件的閘極介電層。然而高介電係數材料的先天特性會導致在與傳統互補式矽基金氧半電晶體(CMOSFET)製程整合時產生某些負面的效應,包括閘極結構缺陷的增加,以及外加電壓導致元件特性的劣化,這些都是高介電閘極元件欲進入應用面所面臨亟需改善的問題。
本文主要針對電荷汲引(Charge pumping)以及低頻雜訊(Low frequency noise)兩種量測技術對元件閘極特性做全面的分析,並以元件理論模型推導並探討元件閘極介電層中缺陷的分佈。本文亦運用此量測方式於原子層沉積氮氧矽酸鉿閘極介電層之電晶體元件,分析調變氮化製程對元件效能及可靠度的影響。此外,利用檢驗氮氧矽酸鉿閘極介電層電晶體元件之電壓溫度不穩定性分析,發現氮化製程會導致P型元件產生明顯的可靠度衰退。經由實驗證實,電漿氮化製程相較於熱氮化製程可以有效改善元件的不穩定性。吾人將之歸因於氮化所造成的缺陷密度分佈的不同,為成功的提升電漿氮化元件的介電層品質及可靠度之主因。
With continual downscaling, high-k dielectrics have been proposed to replace the conventional SiO2 in modern microelectronic technology. However, ionic metal oxide natures of high-k materials result in several undesired instability issues when interfacing with silicon and integrated into CMOS processes, including charge trapping near the Si/dielectric interface and stress-induced device characteristic degradation, which have become urgent issues of high-k gated MOS devices.
In this work, we introduce several measurement techniques based on the principle of charge pumping and flicker noise, and carry out a comprehensive analysis of defects within the CMOS gate stack. Applying these techniques we further examine how nitridation processes of ALD-HfSiON gated MOSFETs affect dielectric quality and electronic properties. Moreover, device bias temperature instability effect also being investigated by a constant voltage stress method, and realize that nitridation processes aggravate the reliability of p-type device. We conclude that plasma nitridation brings significant improvement of dielectric film quality and device reliability. This is due to the nitridation-induced trapping centers are mostly away from channel region, which alleviates the nitridation-induced device performance degradation.
Abstract IV
Acknowledgement VIII
Figure Captions XI
Table Captions XIV
Chapter 1 Introduction 1
1.1 History of Semiconductor Devices 1
1.2 General Background 1
1.2.1 Integration of High-k Gate Dielectrics 4
1.2.2 High-k Material Properties as Gate Dielectrics 4
1.3 Thesis Outline 6
Chapter 2 Experiments and Measurements 9
2.1 Charge Pumping Technique 9
2.1.1 Principle of Charge Pumping 10
2.1.2 Ramp Voltage Charge Pumping Method 11
2.1.3 Leakage Examination of Charge Pumping current 14
2.1.4 Border Trap Effect in Charge Pumping Measurement 16
2.1.5 Capture Cross Section and Energy Distribution of Interface State 18
2.2 Low Frequency Noise Measurement 23
2.2.1 Noise Sources in MOSFET devices 23
2.2.2 Flicker Noise Models 24
2.3 Bias Temperature Instability 29
2.3.1 Trap Generation During Bias Temperature Stress 30
Chapter 3 Depth Distribution of Defects of high-k Dielectric Gate Stack by Combining Charge Pumping and Low Frequency Measurement 35
3.1 Introduction 35
3.2 Device Fabrication Process and Measurement Setup 36
3.3 Trap Profile Calculation of Charge Pumping 37
3.4 Results and Discussion 40
Chapter 4 Bias Temperature Instability Improvement of ALD-HfSiON Gate Stack in Advanced MOSFETs with Plasma Nitridation Process 48
4.1 Introduction 48
4.2 Device Fabrication Process and Measurement Setup 48
4.3 Device Characteristic Degradation 49
4.4 Results and Discussion 52
Chapter 5: Conclusion and Future Work 59
5.1 Conclusion 59
5.2 Future Work 60
References 61
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