臺灣博碩士論文加值系統

隨著元件尺寸不斷的微縮，高介電係數材料(High-k material)勢必將取代傳統二氧化矽作為先進半導體製程中元件的閘極介電層。然而高介電係數材料的先天特性會導致在與傳統互補式矽基金氧半電晶體(CMOSFET)製程整合時產生某些負面的效應，包括閘極結構缺陷的增加，以及外加電壓導致元件特性的劣化，這些都是高介電閘極元件欲進入應用面所面臨亟需改善的問題。
本文主要針對電荷汲引(Charge pumping)以及低頻雜訊(Low frequency noise)兩種量測技術對元件閘極特性做全面的分析，並以元件理論模型推導並探討元件閘極介電層中缺陷的分佈。本文亦運用此量測方式於原子層沉積氮氧矽酸鉿閘極介電層之電晶體元件，分析調變氮化製程對元件效能及可靠度的影響。此外，利用檢驗氮氧矽酸鉿閘極介電層電晶體元件之電壓溫度不穩定性分析，發現氮化製程會導致P型元件產生明顯的可靠度衰退。經由實驗證實，電漿氮化製程相較於熱氮化製程可以有效改善元件的不穩定性。吾人將之歸因於氮化所造成的缺陷密度分佈的不同，為成功的提升電漿氮化元件的介電層品質及可靠度之主因。

With continual downscaling, high-k dielectrics have been proposed to replace the conventional SiO2 in modern microelectronic technology. However, ionic metal oxide natures of high-k materials result in several undesired instability issues when interfacing with silicon and integrated into CMOS processes, including charge trapping near the Si/dielectric interface and stress-induced device characteristic degradation, which have become urgent issues of high-k gated MOS devices.
In this work, we introduce several measurement techniques based on the principle of charge pumping and flicker noise, and carry out a comprehensive analysis of defects within the CMOS gate stack. Applying these techniques we further examine how nitridation processes of ALD-HfSiON gated MOSFETs affect dielectric quality and electronic properties. Moreover, device bias temperature instability effect also being investigated by a constant voltage stress method, and realize that nitridation processes aggravate the reliability of p-type device. We conclude that plasma nitridation brings significant improvement of dielectric film quality and device reliability. This is due to the nitridation-induced trapping centers are mostly away from channel region, which alleviates the nitridation-induced device performance degradation.

Abstract IV
Acknowledgement VIII
Figure Captions XI
Table Captions XIV
Chapter 1 Introduction 1
1.1 History of Semiconductor Devices 1
1.2 General Background 1
1.2.1 Integration of High-k Gate Dielectrics 4
1.2.2 High-k Material Properties as Gate Dielectrics 4
1.3 Thesis Outline 6
Chapter 2 Experiments and Measurements 9
2.1 Charge Pumping Technique 9
2.1.1 Principle of Charge Pumping 10
2.1.2 Ramp Voltage Charge Pumping Method 11
2.1.3 Leakage Examination of Charge Pumping current 14
2.1.4 Border Trap Effect in Charge Pumping Measurement 16
2.1.5 Capture Cross Section and Energy Distribution of Interface State 18
2.2 Low Frequency Noise Measurement 23
2.2.1 Noise Sources in MOSFET devices 23
2.2.2 Flicker Noise Models 24
2.3 Bias Temperature Instability 29
2.3.1 Trap Generation During Bias Temperature Stress 30
Chapter 3 Depth Distribution of Defects of high-k Dielectric Gate Stack by Combining Charge Pumping and Low Frequency Measurement 35
3.1 Introduction 35
3.2 Device Fabrication Process and Measurement Setup 36
3.3 Trap Profile Calculation of Charge Pumping 37
3.4 Results and Discussion 40
Chapter 4 Bias Temperature Instability Improvement of ALD-HfSiON Gate Stack in Advanced MOSFETs with Plasma Nitridation Process 48
4.1 Introduction 48
4.2 Device Fabrication Process and Measurement Setup 48
4.3 Device Characteristic Degradation 49
4.4 Results and Discussion 52
Chapter 5: Conclusion and Future Work 59
5.1 Conclusion 59
5.2 Future Work 60
References 61

[1] Y. Taur, D. A. Buchanan, W. Chen, D. J. Frank, K. E. Ismail, S. H. Lo, G. A. Sai-Halaz" R. G. Viswanathan, H. J. C. Wann, S. J. Wind, and H. S. Wong, "CMOS Scaling Into the Nanometer Regime", in Proceedings IEEE, vol. 85, no. 4, pp. 486-504, 1997.
[2] International Technology Roadmap for Semiconductors (ITRS), 2003 Edition.
[3] Wgsimon, “Transistor count and Moore's Law - 2008”, http://en.wikipedia.org.
[4] International Technology Roadmap for semiconductors (ITRS), 2006 Edition.
[5] G. D. Wilk, R. M. Wallace, J. M. Anthony, ” High-k Gate Dielectrics: Current Status and Materials Properties Considerations ”, Journal of Applied Physics, vol. 89, p. 5243, 2001.
[6] G. Lucovsky, J.C. Phillips, “Defects and Defect Relaxation at Internal Interfaces Between High-k Transition Metal and Rare Earth Dielectrics and Interfacial Native Oxides in Metal Oxide Semiconductor (MOS) Structures”, Thin Solid Films, vol. 486, pp. 200-204, 2004.
[7] C. H. Choi, S. J. Rhee, T. S. Jeon, N. Lu, J. H. Sim, R. Clark, M. Niwa and D. L. Kwong, ‘‘Thermally Stable CVD HfOxNy Advanced Gate Dielectrics with Poly-Si Gate Electrode”, IEDM Technical Digest, pp. 857-860, 2002.
[8] C. S. Kang, H.-J. Cho, K. Onishi, R. Choi, Y. H. Kim, R. Nieh, J. Han, S. Krishnan, A. Shahriar, and J. C. Lee, “Nitrogen concentration effects and performance improvement of MOSFETs using thermally stable HfOxNy gate dielectrics”, Electron Devices Meeting Technical Digest International, pp. 865-868, 2002.
[9] M. R, Visokay, J. J. Chambers, A. L. P. Rotondaro, A. Shanware, and L. Colombo, “Application of HfSiON as a gate dielectric material”, Applied Physics Letter, vol. 80, p. 3183, 2002.
[10] P. D. Kirsch, M. A. Quevedo-Lopez, S. A. Krishnan, B. H. Lee, G. Pant, M. J. Kim, R. M. Wallace, and B. E. Gnade, “Mobility and charge trapping comparison for crystalline and amorphous HfON and HfSiON gate dielectrics”, Applied Physics Letters, vol. 89, p. 242, 2006.
[11] Hei Wong and Hiroshi Iwai, “On the scaling issues and high-j replacement of ultrathin gate dielectrics for nanoscale MOS transistors” Microelectronic Engineering vol.83, pp.1867-1904, 2006.
[12] Kaushik, Vidya S., Nguyen, Bich-yen, Adetutu, Olubunmi O., Hobbs, Christopher C., “Process for forming a high-k gate dielectric”, U.S. Patern, No. 6,184,072.
[13] András Stirling, Alfredo Pasquarello, J.-C. Charlier and Roberto Car, “Dangling Bond Defects at Si-SiO2 Interfaces: Atomic Structure of the Pb Center”, Physical Review Letters, vol. 85, no.13, September 2000.
[14] V V Afanas’ev and A Stesmans, “Charge state of paramagnetic E’ centre in thermal SiO2 layers on silicon”, Journal of Physics: Condensed Matter, vol. 12, pp. 2285-2290, 2000.
[15] Daniel M. Fleetwood , “Border Traps in MOS Devices”, IEEE Transactions on Nuclear Science, vol. 39, no. 2, April 1992.
[16] J. S. Brugler and P. G. Jespers, “Charge pumping in MOS-devices”, IEEE Transactions on Electron Devices, vol. ED-16, p. 297, 1969.
[17] A. B. M. Elliot, “The use of charge pumping currents to measure surface state densities in MOS-transistors”, Solid-State Electronics, vol. 19, p. 241, 1976.
[18] G. Groeseneken, H. E. Maes, N. Beltran, and R. F. De Keersmaecker, “A reliable approach to charge pumping measurements in MOS-transistors”, IEEE Transactions on Electron Devices, vol. ED-31, p. 42, 1984.
[19] U. Cilingiroglu, “A general model for interface trap charge pumping effects in MOS-devices”, Solid-State Electronics, vol. 28, p. 1127, 1985.
[20] W. L. Tseng, “A new charge pumping method of measuring Si-SiO2 interface states”, Journal of Applied Physics, vol. 62, p. 591, 1987.
[21] G. Groeseneken, H. E. Maes, N. Beltran, and R. F. DeKeersmaecker, “The Energy Distribution of Si/SiO2 Interface States Measured in Small Size MOSFETs Using the Charge Pumping Technique”, Insulating Films on Semiconductors Conference, p. 153, 1983.
[22] Ga-Won Lee, Jae-Hee Lee, Hae-Wang Lee, Myoung-Kyu Park, Dae-Gwan Kang, and Hee-Koo Youn, “Trap evaluations of metal/oxide/silicon field-effect transistors with high-k gate dielectric using charge pumping method”, Applied Physics Letters, vol. 81, p. 2050, 2002.
[23] R. E. Paulsen, R. R. Siergiej, M. L. French, and M. H. White, “Observation of Near-Interface Oxide Traps with the Charge-Pumping Technique”, IEEE Electron Device Letter vol.13, p.627, 1992.
[24] R.E. Paulsen, and Marvin H. White, “Theory and Application of charge Pumping for the Characterization of Si-SiO2 interface and near interface Oxide Traps”, IEEE Transactions Electron Devices, ED-41, p.1213, 1994.
[25] Guido Groeseneken, Herman E. Maes, Nicolas Beltran, and Roger F. De keersmaecker, “A Reliable Approach to Charge-Pumping Measurements in MOS Transistors”, IEEE Transactions on Electron Devices, vol. ED-31, no. 1, January 1984.
[26] Han, J.-P. Vogel, E.M. Gusev, E.P. D'Emic, C. Richter, C.A. Heh, D.W. Suehle, J.S. “Energy Distribution of Interface Traps in High-k Gated MOSFETs”, Symposium on VLSl Technology Digest of Technical Papers 2003, pp. 161-162.
[27] S. Christensson, I. LundstrÄom, and C. Svensson, “Low frequency noise in MOS transistors I, theory”, Solid-State Electronics, vol. 11, pp. 797-812, 1968.
[28] S. Christensson and I. LundstrÄom, “Low frequency noise in MOS transistors – II, experiments”, Solid-State Electronics, vol. 11, pp. 813-820, 1968.
[29] G. Reimbold, “Modified 1/f trapping noise theory and experiments in MOS transistors biased from weak to strong inversion - influence of interface states, IEEE Transactions on Electron Devices, vol. 31, pp. 1190-1198, September 1984.
[30] Gerard Ghibaudo, “A simple derivation of Reimbold's drain current spectrum formula for flicker noise in MOSFETs”, Solid-State Electronics, vol.30, pp.1037-1038, October 1987.
[31] F. N. Hooge, “1/f noise is no surface effect”, Physics Letters, vol.29A (3), pp.139-140, April 1969.
[32] F. N. Hooge and L. K. J. Vandamme, “Lattice scattering causes 1/f noise”, Physics Letters, vol.66A, pp.315-316, May 1978.
[33] R. P. Jindal and A. van der Ziel, “Phonon fluctuation model for flicker noise in elemental semiconductors”, Journal of Applied Physics, vol.52(4), pp.2884-2888, April, 1981.
[34] L. K. J. Vandamme and H. M. M. de Werd, “1/f noise model for MOSTs biased in the nonohmic region. Solid-State Electronics”, vol.23(4), pp.325-329, April 1980.
[35] Jayaraman R., Sodini C.G. “A 1 /f Noise Technique to Extract the Oxide Trap Density Near the Conduction Band Edge of Silicon”, IEEE Transactions on Electron Devices, vol. 36, no. 9, September 1989.
[36] Shigeo Ogawa, Masakazu Shimaya, and Noboru Shiono, “Interface-trap generation at ultrathin SiO2(4-6nm)-Si interface during negative-bias temperature aging”, Journal of Applied Physics vol.77, no. 3, p. 1, February 1995.
[37] Yount J.T., Lenahan P.M., Krick J.T., “Comparison of defect structure in N2O- and NH3-nitrided oxide dielectrics” Journal of Applied Physics, vol. 76, p. 1754, 1994.
[38] William L. Warren, P. M. Lenahan, and Sean E. Curry, “First observation of paramagnetic nitrogen dangling-bond centers in silicon nitride”, Physical Review Letters, vol. 65, pp. 207-210, 1990.
[39] J. W. McPherson, R. B. Khamankar, and A. Shanware, “Complementary model for intrinsic time-dependent dielectric breakdown in SiO2 dielectrics”, Journal of Applied Physics, vol. 88, p. 5351, 2000.
[40] Hess K., Haggag A., McMahon W, Fischer B., Cheng K., Lee J., Lyding J., “ Simulation of Si-SiO2 defect generation in CMOS chips: from atomistic structure to chip failure rates“, Electron Devices Meeting Technical Digest International, p. 93, 2000.
[41] Wenjuan Zhu, Jin-Ping Han, and T. P. Ma,” Mobility Measurement and Degradation Mechanisms of MOSFETs MadeWith Ultrathin High-k Dielectrics”, IEEE Transactions on Electron Devices, vol. 51, no. 1, January 2004.
[42] A. Kerber, E. Cartier, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, A. Hou, G. GroesenekenE, H. E. Maes, and U. Schwalke, “Origin of the Threshold Voltage Instability in SiO2/HfO2 Dual Layer Gate Dielectrics”, IEEE Electron Device Letters, vol. 24, no. 2, February 2003.
[43] Howrad C.-H. Wang, Shang-Jr Chen, Ming-Fang Wang, Pang-Yen Tsai, Ching-Wei Tsai. Ta-Wei Wang, Steve M. Ting, Tuo-Hung Hou, Peng-Soon Lim, Huan-Just Lin, Ying Jin, Hun-Jan Tao, Shih-Chang Chen, Carlos H. Diaz, Mong-Song Liang, and Chenming Hu, “Low Power Device Technology with SiGe Channel, HfSiON, and Poly-Si Gate”, Electron Devices Meeting Technical Digest International, p. 161, 2004.
[44] Y. Yasuda, N. Kimizuka, T. Iwamoto, S. Fujieda, T. Ogura, H. Watanabe, T. Tatsumi, I. Yamamoto, K. Ita, H. Watanabe, Y. Yamagata, and K. Imai, “A 65nm-node LSTP (Low Standby Power) Poly-Si/a-Si/HfSiON Transistor with High Ion-Istandby Ratio and Reliability”, Symposium on VLSl Technology Digest, p. 40, 2004.
[45] Shinji Fujieda, Setsu Kotsuji, Ayuka Morioka, Masayuki Terai and Motofumi Saitoh, “Influence of Charge Traps within HfSiON Bulk on Positive and Negative Bias Temperature Instability of HfSiON Gate Stacks”, Japanese Journal of Applied Physics, vol. 44, p. 2385, 2005.
[46] B. Djezzar, A. Smatti, and S. Qussalah, “A new oxide-trap based on charge-pumping (OTCP) extraction method for irradiated MOSFET device—Part II (Low Frequencies),” IEEE Transactions on Nuclear Science, vol. 51, no. 4, pp. 1732-1736, August 2004.
[47] Y. Maneglia and D. Bauza, “Extraction of slow oxide trap concentration profiles in metal–oxide–semiconductor transistors using the charge pumping method”, Journal of Applied Physics, vol.79(8), p.15, 1996.
[48] Eddy Simoen, A. Mercha, L. Pantisano, Cor Claeys, and E. Young, ” Low-Frequency Noise Behavior of SiO2–HfO2 Dual-Layer Gate Dielectric nMOSFETs With Different Interfacial Oxide Thickness”, IEEE Transactions on Electron Devices, vol. 51, no. 4, p. 780, 2004.
[49] F. P. Heiman and G. Warfield, “The Effect of Oxide Traps in MOS Capacitance”, IEEE Transactions on Electron Devices, vol. ED-12, p. 167, 1965.
[50] Inumiya, S.; Akasaka, Y.; Matsuki, T.; Ootsuka, F.; Torii, K.; Nara, Y. ”A thermally-stable sub-0.9nm EOT TaSix/HfSiON Gate Stack With High Electron Mobility, Suitable for Gate-First Fabrciation of Hp45 LOP Devices”, Electron Devices Meeting Technical Digest. IEEE International, vol. 5, issue 5, pp. 23-26, December 2005.
[51] Siddarth A. Krishnan, Manuel Quevedo-Lopez, Hong-Jyh Li, Paul Kirsch, Rino Choi, Chadwin Young, Jeff J. Peterson, Byoung Hun Lee, Gennadi Bersuker and Jack C. Lee, “Impact of Nitrogen on PBTI Characteristics of HfSiON/TiN Gate Stacks”, IEEE Reliability Physics Symposium Proceedings, pp.325-328, 2004.
[52] Chun-Yuan Lu, Kuei-Shu Chang-Liao, Ping-Hung Tsai, and Tien-Ko Wang, “Depth Profiling of Border Traps in MOSFET With High-k Gate Dielectric by Charge-Pumping Technique”, IEEE Electron Device Letters, vol. 27, no. 10, October 2006.
[53] T. Horikawa, N. Yasuda, W. Mizubayashi, K. Iwamoto, K. Tominaga, K. Akiyama, K. Yamamoto, H. Hisamatsu, H. Ota, T. Nabatame, A. Toriumi, "Low Frequency Noise Characterization in HfAlOx/SiO2 n-MOSFETs", Proceeding Volumes for Electrochemical Society Meeting, vol. 01, pp. 292-303, 2004.
[54] E. Simoen, A. Mercha, L. Pantisano, C. Claeys, and E. Young, “Low Frequency Noise Behavoir of SiO2-HfO2 Dual Layer Gate Dielectric nMOSFETs with Different Interfacial Oxide Thickness”, IEEE Transactions on Electron Devices, vol. 51, no. 5, May 2004.
[55] E. Simoen, A. Mercha, L. Pantisano, C. Claeys, E. Young, “Tunneling 1/f�� noise in 5 nm HfO2/2.1 nm SiO2 gate stack”, Solid-State Electronics vol. 49, pp. 702-707, 2005.
[56] K. O. Jeppson and C. M. Svensson, “Negative Bias Stress of MOS Devices at High Electric Fields and Degradation of MNOS Devices,” Journal of Applied Physics, vol. 48, no. 5, pp. 2004-2014, May 1977.
[57] S. Ogawa and N. Shiono, “Generalized Diffusion-Reaction Model for the Low-Field Charge-Buildup Instability at the Si-SiO2 Interface”, Physical Review B - condensed matter and materials physics, vol. 51, no. 7, pp. 4218-4230, February 1995.