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研究生:吳尚勳
研究生(外文):Shang-Hsun Wu
論文名稱:應用於多標準載波產生器之超低功率變壓器架構振盪器的設計與實現
論文名稱(外文):Design and Implementation of Ultra Low Power Transformer-Based Oscillators for Multi-Standard Carrier Generators
指導教授:黃尊禧
指導教授(外文):Tzuen-Hsi Huang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:143
中文關鍵詞:變壓器回授共存變壓器耦合除三電路電流重複使用振盪器
外文關鍵詞:divide-by-three circuitcurrent-reusedtransformer-coupledoscillatorstransformer-feedbackco-existent
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本論文針對802.11a/g和MB-OFDM超寬頻(Ultra-Wideband, UWB)的系統共存應用提出載波頻率合成規劃。而本論文主要針對系統規劃中所需7-GHz四相位信號產生器尋求低功率消耗的解決方案,其中所採用的關鍵技術主要包含變壓器耦合(Transformer-Coupled)搭配電流重複使用(Current-Reused)技術來實現高效能的振盪器。
本論文第一部分提出平面全對稱變壓器佈局架構,其中將次線圈交錯於主線圈中間以提昇磁耦合(Mutual Magnetic Coupling)因子,並且同步使用並聯橋接(Parallel Bridge Connection)方式來實現主副線圈比,最後和其它兩種不同架構變壓器進行特性比較;第二部份則是將所提的全對稱變壓器應用於創新振盪器設計之中,主要包含有變壓器回授(Transformer-Feedback)電流重複使用差動式振盪器,和變壓器串接交錯耦合電流重複使用的四相位振盪器,晶片製作均使用TSMC 0.18 μm CMOS 製程技術,本論文中詳細的說明電路原理和設計考量。
以下就論文中三個振盪器電路的量測結果做說明,第一個低功率消耗寬頻差動式振盪器的量測結果顯示,輸出頻率從7.07-8.46-GHz,擁有1.39GHz的頻寬(17.9 %可調百分比),在8.1 GHz時,輸出功率約為-8.45 dBm,相位雜訊為-112.05 dBc/Hz@1-MHz,在電源為1.5 V時功率消耗為2.16 mW。第二個低功率消耗高效能四相位振盪器的量測結果顯示,輸出頻率從7.1-7.62-GHz擁有510 MHz的頻寬,在7.26 GHz時,輸出功率約為-10.63 dBm,相位雜訊為-111.4 dBc/Hz@1-MHz,在電源為1 V時功率消耗為1.58 mW,相位誤差小於1度。
第三個應用於K-Band頻段低功率消耗高效能四相位振盪器的量測結果顯示,輸出頻率從21.75-22.28-GHz,擁有525 MHz的頻寬,在21.8 GHz時,輸出功率約為-14.35 dBm,相位雜訊為-102.5 dBc/Hz@1-MHz,在電源為1.5 V時功率消耗為3.9 mW。最後,附錄部份為高創新度的真實單相時脈(True Single-Phase Clocked, TSPC)四相位除三(Quadrature Divide-by-Three)電路。主要應用於本實驗室提出802.11a/g和MB-OFDM UWB共存載波系統所需的除三電路方塊;此技術亦可用於任何多標準載波頻率合成規劃之中。根據量測結果顯示,此電路架構確實輸出四相位、接近50%對稱性脈波寬(50% duty-cycle pulse width)之除三時脈訊號。
This thesis presents a multi-standard carrier frequency planning synthesizer for 802.11a/g and MB-OFDM UWB co-existent applications. We mainly research in the solution of the low dc power dissipation for the needed 7-GHz band quadrature signal generator in the proposed carrier generation system in this thesis. It mainly adopts critical techniques including both the transformer-coupled and the current-reused to achieve high performance oscillators.
Firstly, the plane transformer is analyzed in this thesis. A fully symmetric differential transformer structure is proposed to increase mutual magnetic coupling factor through the secondary coil interlaced among the primary coil. In addition, the secondary coil is paralleled cross-connection to reach symmetry and appropriate turn ratio. The measured characteristics of proposed fully transformer are compared with other structures in chip testkey.
Secondly, the novel voltage-controlled oscillators (VCOs) are implemented to achieve low phase noise under lower dc power consumption by the proposed fully symmetric transformer combination of the current-reused cross-coupled core. They include the transformer-feedback current-reused differential VCO and the transformer series-coupled current-reused quadrature VCO. These chips are fabricated by TSMC 0.18 μm CMOS process. The principle and design consideration of these circuit are described completely in thesis.
In the following, we discussed the measured results of three oscillators. The low power consumption wideband differential VCO can operate from 7.07GHz to 8.46 GHz. It has the 1.39 GHz (17.9 % tuning ratio) frequency tuning range When the VCO operating at 8.1 GHz with the output power is -8.45 dBm, and the measured phase noise at 1-MHz offset is -112.05 dBc/Hz. The power consumption of the VCO core circuit is 2.16 mW at 1.5 V supply voltage. The quadrature VCO with low power consumption and high performance can operate from 7.1GHz to 7.62 GHz. It has 510 MHz bandwidth. When the QVCO operating at 7.26 GHz with the output power is -10.63 dBm, and the measured phase noise at 1-MHz offset is -111.4 dBc/Hz. The power consumption of the QVCO core circuit is 1.58 mW at 1 V supply voltage. Phase deviation is less than 1 degree. The K-Band quadrature VCO with low power consumption and high performance can operate from 21.75 GHz to 22.28 GHz. It has 525 MHz bandwidth. When the QVCO operating at 21.8 GHz with the output power is -14.35 dBm, and the measured phase noise at 1-MHz offset is -102.5 dBc/Hz. The power consumption of the QVCO core circuit is 3.9 mW at 1.5 V supply voltage.
Finally, the appendix A is novel true single-phase clocked quadrature divide-by-three circuit. It is mainly applied in the desired divide-by-three block of the proposed 802.11a/g and MB-OFDM UWB co-existence carrier system. This technology is also applied to the any multi-standard carrier frequency planning. According to the measured results, this circuit can achieve divide-by-three function and have the quadrature phase waveforms close to 50% duty-cycle pulse width.
摘 要.... .I
Abstract.....III
List of Tables.....X
List of Figures..... XI
Chapter 1 Introduction.....1
1-1 Background.....1
1-2 Motivation.....3
1-3 Thesis Organization..... 5
Chapter 2 Passive Component.....7
2-1 Varactor.....7
2-1-1 MOS Varactor.....7
2-1-2 Inversion-Mode MOS Varactor.....8
2-1-3 Accumulation-Mode MOS Varactor .....10
2-2 Inductor Model Extraction.....11
2-2-1 The TSMC Inductor Model.....12
2-2-2 The Inductor Model Extraction from Y parameters.....13
2-2-3 Extraction of series Ls and Rs.....14
2-2-4 Extraction of Cp.....18
2-2-5 Extraction of the Substrate Network..... 19
2-3 LC-Tank..... 25
2-3-1 Quality Factor (Q).....25
2-3-2 Series R-L Network.....27
2-3-3 Series R-C Network.....28
2-3-4 The Quality Factor of LC Tank.....29
Chapter 3 On-Chip Transformer.....35
3-1 Introduction.....35
3-2 Physical Property.....36
3-3 The Characteristic Target of Transformer.....38
3-4 Transformer Design and Layout..... 41
3-4-1 Apply in VCO and QVCO of Transformer.....41
3-4-2 Concentric Transformer.....42
3-4-3 Parallel Transformer.....43
3-4-4 Parallel Balanced Transformer.....43
3-5 Simulated and Measured Results.....44
3-5-1 Test-key.....44
3-5-2 Measurement Scheme.....46
3-5-3 Concentric Transformer (TRF-2).....46
3-5-4 Parallel Transformer (TRF-3).....50
3-5-5 Parallel Balanced Transformer (TRF-5).....53
Chapter 4 Current-Reuse Transformer-Feedback VCO.....57
4-1 Introduction.....57
4-2 Transformer-Feedback Architecture.....57
4-3 Current-Reuse Architecture.....59
4-4 Switch Capacitor Arrays (SCAs) Architecture.....63
4-5 The proposed CR_TF_Wideband VCO.....69
4-6 Design Process .....71
4-7 Transformer Simulation Results.....72
4-8 VCO Simulation Results.....73
4-8-1 Switch-11 (Vsw_2 → ON , Vsw_1 → ON).....73
4-8-2 Switch-10 (Vsw_2 → ON , Vsw_1 → OFF).....75
4-8-3 Switch-01 (Vsw_2 → OFF , Vsw_1 → ON).....77
4-8-4 Switch-00 (Vsw_2 → OFF , Vsw_1 → OFF).....79
4-8-5 Overall Tuning Range .....81
4-8-6 Layout of Proposed VCO.....81
4-9 Measured Results.....82
4-9-1 Measurement Consideration and Equipments.....82
4-9-2 Overall Tuning Range .....83
4-9-3 Phase noise.....85
4-9-4 Specifications.....88
Chapter 5 Current-Reuse Transformer-Coupled QVCO.....92
5-1 Introduction.....92
5-1-1 Transformer-Coupled QVCO.....93
5-2 The proposed Current-Reused Transformer-Coupled QVCO.....94
5-2-1 CR-TC-QVCO Core Design Issue.....95
5-2-2 On-Chip Trifilar Transformer Design..... 96
5-3 Design Process .....98
5-4 Simulation Results.....99
5-4-1 Transformer Simulation Results .....99
5-4-2 CR-TC-QVCO Simulation Results .....100
5-4-3 Layout of Proposed QVCO.....102
5-5 Measured Results.....103
5-5-1 Measurement Consideration and Equipments.....103
5-5-2 Tuning Range.....104
5-5-3 Phase noise.....105
5-5-4 Specifications.....107
5-6 K-Band Current-Reused Transformer-Coupled QVCO.....109
5-6-1 CR-TC-QVCO Core Design Issue.....109
5-6-2 On-Chip Stacked Transformer Design.....110
5-7 Simulation Results.....112
5-7-1 Stacked Transformer Simulation Results.....112
5-7-2 K-Band CR-TC-QVCO Simulation Results.....113
5-7-3 Layout of Proposed K-Band QVCO.....115
5-8 Measured Results.....116
5-8-1 Measurement Consideration and Equipments.....116
5-8-2 Tuning Range.....118
5-8-3 Phase noise.....118
5-8-4 Specifications.....120
Chapter 6 Conclusion and Future Work.....122
6-1 Conclusion.....122
6-2 Future Work.....124
Appendix A TSPC Quadrature Divide-by-Three Circuit.....126
A-1 Introduction.....126
A-2 Architecture.....127
A-2-1 3,168 MHz PMOS Only VCO.....128
A-2-2 Current Mode Logic Divide-by-Two Circuit.....129
A-2-3 Sinusoid-to-Square Transformation Circuit.....130
A-2-4 TSPC Quadrature Divide-by-Three Circuit.....130
A-3 Simulation Results.....132
A-4 Measured Results.....136
Reference.....139
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[62] Bo Sun, “Divide-by-three circuit,” US patent, patent no. 6,389,095. (May 14, 2002).
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