臺灣博碩士論文加值系統

　　在本篇論文中，我們主要著眼於開發設計一個低電壓低功率的米勒除三電路。此電路整合了三個子電路區塊，分別是一個操作頻率為1584 MHz的四相位輸出壓控震盪器(QVCO)、一個單邊側頻帶(Single-sideband；SSB)混頻器和一個採用電流型邏輯電路(Current mode logic；CML)的數位式除二電路。由文獻可知，以上三個電路連接成一個回授電路，可以得到一個米勒架構型式的除三功能電路。
　　由於此米勒除三電路的目的是要應用於超寬頻(UWB)射頻頻率合成器中，因此必須符合下列兩個要素，具有四相位訊號輸出以提供頻率合成器裡的SSB混頻器區塊使用和具有50%的輸出振幅週期(duty-cycle)以確保輸出訊號能在混頻器中產生較純淨的頻譜。此外，由於除三電路中應用數位式的除頻器到較高的操作頻率下，因此造成很大的功率損耗。然而現今的應用電路講求低電壓操作以提高電路效能，故設計一個操作在低電壓的除三電路且降低功率損耗，將是本論文的主要訴求。
　　為了實現低電壓操作的米勒除三電路，本論文中的單邊側頻帶混頻器採用了電流重複使用(Current reuse)的設計概念。藉由電路折疊架構並給定適當的偏壓，可以大大的降低電路的供應電壓需求以達低電壓操作的目的。另外，本論文中的除二電路採用了電流型邏輯電路的除頻器，不外乎是因為它天生可以輸出四相位訊號，但電晶體堆疊級數之故其操作電壓往往高於1.5伏特。因此在我們的電路架構中，改變了電晶體的配置以減少電路堆疊(stack)的級數，而降低電路的操作電壓以達本論文的設計目標。至於四相位輸出的壓控震盪器，在本論文中則是扮演了兩個角色：第一、直接驗證此除三電路是否可正常提供528 MHz 頻率輸出。藉由改變壓控震盪器的震盪頻率，觀察米勒除三電路的輸出是否有達到將震盪頻率除以三的功能；第二、方便電路的量測。因為單邊側頻帶(Single-sideband；SSB)混頻器需要四相位的輸入訊號，而產生四相位訊號的訊號產生器不易取得，所以我們直接整合一個四相位輸出的壓控震盪器在此電路中。
　　就我們所知，在大部份超寬頻多頻帶正交頻率分頻多工(MB-OFDM)的系統頻帶規劃中，如欲產生完整的14個次頻帶載波(sub-band carriers)頻率訊號，且相鄰的兩個次頻帶其載波頻率皆為528 MHz，除三電路是系統中不可或缺的。故本論文的貢獻就是在於開發一個可以產生528 MHz輸出頻率並以米勒型式建構而成的除三電路，且此電路不但具有四相位訊號輸出以及輸出波形擁有50%振幅週期(duty-cycle)的特性，還可以操作在相當低的供應電壓以降低電路整體的功率損耗。總體而言，我們成功地開發設計了一個操作在1.2伏特，消耗功率約27mW，可輸出528MHz四相位訊號的除三電路。且除頻範圍在1464MHz到1788MHz，可得的輸出頻率範圍有108MHz，相當於操作頻率的20%。

　　The main part of this thesis is concerns the design of a Miller divide-by-three circuit with low supply voltage and low power consumption. The circuit consists of three function blocks such as a quadrature voltage-controlled oscillator (QVCO), a single-sideband (SSB) mixer and a digital divide-by-two circuit with current mode logic (CML) technique. According to the references, we can construct a Miller divide-by-three circuit by connecting the above three function blocks in a feedback loop.
　　Since the purpose of this Miller divide-by-three circuit is applied to the UWB RF frequency synthesizers, it must satisfy the following character, generating quadrature output waveform with 50% duty cycle for the SSB mixer to have a purer output spectrum. Furthermore, a classical divide-by-three circuit is hungry for power consumption because the digital divide-by-two circuit is integrated inside to raise the operation frequency. Therefore, for considering the low voltage application to extend the battery life in a portable system, the circuit design demands the implementation of our divide-by-three circuit with a low supply voltage and low power consumption.
　　In order to construct a Miller divide-by-three circuit with low operation voltage, the concept of current reuse technique is applied to the SSB mixer in this paper. Through the proper bias design with the folded structure, the supply voltage can be reduced by a large amount. On the other hand, the CML divide-by-two circuit is adopted in this paper since the quadrature outputs can be generated naturally, but the operation voltage is more than 1.5V due to the stacks of transistors. Thus, we replaced the parallel current switching PMOS transistors for the conventional NMOS stacked switching stage to reduce the supply voltage. The quadrature voltage-controlled oscillator plays two parts of roles in our circuit. First, to verify if the divide-by-three function of the proposed circuit can normally provide 528 MHz output, and second, to make our measurement be more convenient since the quadrature signal generator is not easy to get.
　　As far as the author’s knowledge, according to the proposed frequency plans, a divide-by-three circuit is indispensable to the MB-OFDM UWB system in generating full fourteen sub-band carrier signals with each carrier being separated by 528 MHz. Thus, the contribution of this thesis is developing a Miller divide-by-three circuit with 528 MHz output frequency, and such a circuit not only can generate quadrature output signals with 50% duty cycle waveform, but also can operate properly within a low supply voltage and the power consumption is thus greatly reduced. In sum, we developed a Miller divide-by-three circuit with 1.2V supply voltage and about 27mW power consumption. Furthermore, this circuit performs an operation frequency range from 1464MHz to 1788MHz with 108MHz output frequency range.

Content

Abstract in Chinese...........I
Abstract in English...........III
Acknowledgement...........V
Content...........VI
List of Tables...........VIII
List of Figures...........IX

Chapter 1 Introduction...........1
1.1 Background...........1
1.1.1 Ultra-wideband Technology...........1
1.1.2 Applications...........3
1.2 Motivation...........6
1.3 Thesis Organization...........10
Chapter 2 Frequency Divider...........11
2.1 Circuit Principle...........11
2.1.1 Building Blocks...........11
2.1.2 Static and Dynamic Frequency Dividers...........15
2.2 Topology...........19
2.2.1 True Single-phase-clock Circuits...........19
2.2.2 Current Mode Logic Circuits...........23
2.2.3 Injection-locked Frequency Dividers...........27
2.3 Divide-by-three circuit...........31
Chapter 3 Circuit Implementation...........36
3.1 Miller Divide-by-three Circuit...........36
3.2 Circuit Design Flow...........39
3.2.1 Quadrature voltage-controlled Oscillator...........41
3.2.2 Single-sideband Mixer...........49
3.2.3 Divide-by-two Circuit...........56
3.3 The First Chip of Miller Divide-by-three Circuit........... 58
3.3.1 Architecture...........58
3.3.2 Simulation and Measurement Results...........65
3.3.3 Verifications of Problems...........75
3.4 The Second Chip of Miller Divide-by-three Circuit...........78
3.4.1 Architecture...........78
3.4.2 Simulation Results ...........83
Chapter 4 Measurement Results...........90
4.1 Measurement Considerations...........90
4.2 Measurement Results...........92
Chapter 5 Conclusion...........102
5.1 Summary...........102
5.2 Future Work...........104

References...........105

List of Tables

Table 1.1 The lists of features of MB-OFDM and DS-CDMA systems...........5
Table 3.1 The expected specifications of the quadrature VCO...........68
Table 3.2 The expected specifications table for Miller divide-by-three circuit...........71
Table 3.3 The expected specifications of the quadrature VCO...........86
Table 3.4 The expected specifications table for Miller divide-by-three circuit...........89
Table 4.1 The post-simulation results under 1V and 1.2V supply voltage...........92
Table 4.2 The performance of the proposed Miller divide-by-three circuit...........101
Table 4.3 The comparison with other papers...........101

UList of Figures

Figure 1.1 The position of UWB comparing with other wireless technology...........2
Figure 1.2 Spectrums of (a)DS-CDMA system and (b)MB-OFDM system...........4
Figure 1.3 UWB frequency synthesizers proposed in [22] with a divide-by-three function block which is highlighted...........6
Figure 1.4 The frequency tree diagram...........8
Figure 1.5 The block diagram of the proposed Miller divide-by-three circuit...........9
Figure 2.1 (a)The symbol of the Data flip-flop
(b)The block diagram of the Data flip-flop...........12
Figure 2.2 The timing diagram of the signal of a Data flip-flop ...........13
Figure 2.3 The circuit level of a single latch...........13
Figure 2.4 The symbol of a Toggle flip-flop...........14
Figure 2.5 The timing diagram of the signal of a Toggle flip-flop...........14
Figure 2.6 The block diagram of a static frequency divider...........16
Figure 2.7 The block diagram of a dynamic frequency divider...........16
Figure 2.8 The mixer of a conventional dynamic frequency divider...........18
Figure 2.9 The circuitry of RF-port feedback and LO-port feedback...........18
Figure 2.10 The clocked CMOS logic (C2MOS)...........19
Figure 2.11 NORA dynamic CMOS technique (Phi-section with N-precharge block)...........20
Figure 2.12 The true single-phase-clock latch (double N-C2MOS)...........21
Figure 2.13 (a)The D-type flip-flop (positive transition latch)(b)The divide-by-two circuit...........21
Figure 2.14 (a)The D-type flip-flop constructed by split-output latch stages(b)The divide-by-two circuit constructed by split-output latch stages...........22
Figure 2.15 (a)The inverter of the CMOS logic(b)The inverter of the current mode logic (CML)...........24
Figure 2.16 The schematic of a current mode logic (CML) D-latch...........25
Figure 2.17 The schematic of a CML divide-by-two frequency divider...........26
Figure 2.18 An injection-locked frequency divider based on
(a)the complementary oscillator(b)the Colpitts oscillator(c)the ring oscillator...........29
Figure 2.19 The injection-locked frequency divider with tunable active inductors...........30


Figure 2.20 (a)The conventional divide-by-three circuit (b)The negatively triggered sample-hold-hold (SHH) divide-by-three circuit based on current switchable D flip-flops and its timing diagram...........32
Figure 2.21 The schematic of a current switchable D flip-flop...........33
Figure 2.22 The quadrature divide-by-three circuit...........34
Figure 2.23 The ring-based injection-locked divide-by-three circuit...........34
Figure 2.24 The diagram of a Miller divide-by-three circuit...........35
Figure 3.1 The overall circuit schematic of the Miller divide-by-three circuit...........37
Figure 3.2 Miller divider ...........38
Figure 3.3 A negative feedback system...........41
Figure 3.4 A divide-by-two circuit...........42
Figure 3.5 A ring oscillator with quadrature outputs...........43
Figure 3.6 The phase diagram of the ring circuit...........44
Figure 3.7 The RC-CR phase shift circuit...........45
Figure 3.8 The improved RC-CR phase shift structure...........47
Figure 3.9 The typical cross-coupled qiadrature VCO...........48
Figure 3.10 The typical series type cross-coupled quadrature VCO...........49
Figure 3.11 The symbol of a mixer...........50
Figure 3.12 Frequency spectrum of the mixer...........51
Figure 3.13 Frequency spectrum of single-sideband mixers...........52
Figure 3.14 The single-sideband mixer with an LC tank loading stage...........54
Figure 3.15 The Q-enhanced circuit...........55
Figure 3.16 Divide-by-two circuits with(a)True single-phase-clock (TSPC) technique...........56
(b)Current mode logic (CML) technique(c)Injection locked frequency divider (ILFD)...........57
Figure 3.17 The QVCO of the first chip...........58
Figure 3.18 The single-sideband mixer...........60
Figure 3.19 The adopted current reuse circuit...........61
Figure 3.20 The improved D flip-flop of the divide-by-two circuit...........62
Figure 3.21 The layout of the proposed Miller divide-by-three circuit...........64
Figure 3.22 The transient response of the quadrature VCO...........65
Figure 3.23 The frequency spectrum of the quadrature VCO...........66
Figure 3.24 The phase noise of the quadrature VCO...........66
Figure 3.25 The tuning range of the quadrature VCO...........67
Figure 3.26 The transient response of the Miller divide-by-three circuit...........69
Figure 3.27 The frequency spectrum of the quadrature VCO...........69
Figure 3.28 The frequency spectrum of the Miller divide-by-three circuit...........70
Figure 3.29 The quadrature output waveform of the Miller divide-by-three circuit...........70
Figure 3.30 The picture of our PCB board for measuring...........72
Figure 3.31 The output frequency generated by quadrature VCO only...........73
Figure 3.32 The output frequency spectrum of the divide-by-three circuit...........74
Figure 3.33 The output frequency of the quadrature VCO at tuning voltage equal to 0V...........75
Figure 3.34 The output frequency of the quadrature VCO at tuning voltage equal to 1.2V...........76
Figure 3.35 The frequency spectrum of the single-sideband mixer only...........77
Figure 3.36 The schematic of the quadrature VCO of the second chip...........79
Figure 3.37 The single-sideband mixer of the second chip...........80
Figure 3.38 The improved divide-by-two circuit...........81
Figure 3.39 The layout view of the second chip...........82
Figure 3.40 The transient response of the quadrature VCO...........83
Figure 3.41 The frequency spectrum of the quadrature VCO...........84
Figure 3.42 The phase noise of the quadrature VCO...........84
Figure 3.43 The tuning rage of the quadrature VCO...........85
Figure 3.44 The transient response of the Miller divide-by-three circuit...........87
Figure 3.45 The frequency spectrum of the quadrature VCO...........87
Figure 3.46 The frequency spectrum of the Miller divide-by-three circuit...........88
Figure 3.47 The quadrature output waveform...........88
Figure 4.1 The PCB board of the improved Miller divide-by-three circuit...........90
Figure 4.2 The chip photo of the improved Miller divide-by-three circuit...........91
Figure 4.3 The frequency spectrum of 528 MHz output...........93
Figure 4.4 The phase noise of 528 MHz output...........94
Figure 4.5 The frequency spectrum of the lowest output frequency...........95
Figure 4.6 The phase noise of the lowest output frequency...........95
Figure 4.7 The frequency spectrum of the highest output frequency ...........96
Figure 4.8 The phase noise of the highest output frequency...........97
Figure 4.9 Tuning range, output power and operation current of the Miller divide-by-three circuit...........98
Figure 4.10 The quadrature output waveform...........99
Figure 4.11 The primary frequency and the harmonics...........100

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