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研究生:朱俊杰
研究生(外文):Jun-Jie Zhu
論文名稱:數位訊號處理器之高效率軟體自我測試方法研究
論文名稱(外文):Efficient Software-Based Self-Test Methods for Embedded Digital Signal Processors
指導教授:謝明得謝明得引用關係
指導教授(外文):Ming-Der Shieh
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:73
中文關鍵詞:數位訊號處理器軟體自我測試
外文關鍵詞:functional testingSBSTDSPSoftware-based Self-test
相關次數:
  • 被引用被引用:1
  • 點閱點閱:105
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  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
由於系統單晶片(System-on-a-Chip; SOC)技術在當今電路設計發展愈來愈成熟,因此像是使用雙核心處理器(Dual Core Processor)如ARM與DSP,運用在手機、個人數位產品、數位照相機及消費電子上愈來愈普及,故嵌入式數位訊號處理器在SoC系統上,扮演的角色愈來愈重要。因此針對各種處理器發展出一套有效率的測試方法便是一件重要且實際的問題。相較於傳統以掃瞄鏈(Scan Chain)為基礎的測試方法,軟體功能測試(Software-based self-test)方法不需增加額外面積以及造成效能的下降,並且提供處理器全速(at-speed)執行底下執行測試。但軟體功能測試主要問題在於沒辦法有較高的錯誤涵蓋率(fault coverage)以及需要較多的測試樣本(test vectors),因此如何在不增加面積與不降低效能前提下,有效率的來測試數位訊號處理器,進而提升錯誤涵蓋率,是本論文主要的研究主題。
本篇論文主要包含兩大部份:第一個部份是針對相容於TMS320C54x系列的數位訊號處理器架構之設計。第二個部份為使用混合軟體功能測試方法針對所設計出來的數位訊號處理器作測試。主要方法包含隨機/虛擬隨機(random/psudorandom)產生測試程式,有條件限制之自動樣本產生器(Constrained ATPG),及定義指令集架構(instruction set architecture)的測試模組等方法來測試我們的數位訊號處理器,進而提昇錯誤涵蓋率。由實驗結果顯示使用我們所建議的軟體自我測試方法流程,數位訊號處理器的錯誤涵蓋率可達到百分之九十六以上,而比較目前其他相關的研究,以我們所提出的方法可以得到最高的錯誤涵蓋率。
With rapid development of SoC (System-on-Chip) techniques, dual core processors (ARM and DSP processor) are extensively used in consumer electronics like mobile phone, digital camera, etc. Since the embedded processor plays an important role in SoC, an efficient test method with little overhead and high fault coverage has become a critical issue. Compared with the scan-based test methods, the software-based self-test (SBST) method does not suffer from area overhead and performance degradation, and can provide at-speed test for DSPs with the potential drawbacks of lower fault coverage and a larger amount of test vectors.
This work first presents a DSP processor designs based on TMS320C54x series. Then we propose a hybrid software-based test method for the developed DSP. In the developed SBST method, techniques such as the constrained ATPG, random/pseudorandom patterns, and specific templates for the instruction set architecture are employed to enhance the fault coverage of the DSP core. Experimental results exhibit that applying the developed SBST test flow obtains more than 96% fault coverage for our DSP core, which is higher than the reported values in related works.
中文摘要 i
英文摘要 ii
誌 謝 iii
目  錄 iv
表 目 錄 vii
圖 目 錄 viii
第一章 緒論 1
1.1 研究動機 1
1.2 TI-Compatible DSP處理器架構設計 4
1.3 內容的編排 5
第二章 背景知識之介紹 6
2.1 TI TMS320C54x處理器的介紹 6
2.1.1 CPU狀態和控制暫存器 8
2.1.2記憶體映射暫存器 12
2.1.3 TI TMS320C54x指令集架構 14
2.2 功能性測試 15
第三章TI-Compatible數位信號處理器設計與驗證 16
3.1 TI-Compatible DSP處理器設計之規格 16
3.2 TI-Compatible DSP晶片的特性 19
3.3 TI-Compatible DSP處理器架構設計 21
3.3.1 管線操作 22
3.3.1.1資料危障的處理 23
3.3.2 TI-Compatible DSP定址模式 25
3.4 TI-Compatible DSP驗證架構 34
第四章 測試規劃 38
4.1 測試流程 38
4.2記憶體映射暫存器測試 44
4.3 隨機測試 46
4.3.1 隨機測試樣板 46
4.3.2 運算元串接 49
4.3.3 指令加權 50
4.3.4 自動化移除多餘測試樣本 51
4.4有條件之自動樣本產生器 51
4.4.1模組測試選擇 54
4.5 定址模式測試 56
4.6 回饋測試 56
4.7 管線暫存器測試 58
4.8 可測試設計 59
4.8.1 測試指令 59
4.8.2 虛擬位置產生器 59
4.9 全掃描測試 61
第五章 實驗結果 62
5.1 測試結果 62
5.1.1 隨機測試樣板比較 62
5.1.2自動化移除多餘測試樣本 64
5.1.3 測試結果比較 65
5.2 錯誤分析 66
5.3 比較其它測試方法 68
第六章 結論與未來展望 69
6.1 結論 69
6.2 未來展望 70
參考文獻 71
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