臺灣博碩士論文加值系統

隨著製程技術的演進，基於可靠度的考量，低電壓操作已經變成未來電路的趨勢。然而電路的供應電壓不斷的下降的同時，將會減少訊號的動態範圍。若欲維持一定的動態範圍，必須設法抑制雜訊並降低訊號失真量，如此將間接增加類比電路的功率消耗。在傳統管路式類比數位轉換器的設計中，需要一個極高增益的運算放大器來確保訊號處理的準確性，而製程的限制將使設計這樣的運算放大器面臨極大的困難。本論文提出一個高頻寬取樣保持放大器來克服實現高增益運算放大器所帶來的困難，並且同時提高對於輸入訊號振幅的容忍度。運用所提出的電路技巧，本論文採用台積電0.18微米互補式金氧半製程來設計一個10位元每秒取樣2億次的管路式類比數位轉換器。

With the advance of deep submicron technology, the low supply voltage will become the trend of circuit development due to the device’s reliability issues. However, the signal dynamic range will be decreased because of the reduction of supply voltage. In order to maintain the dynamic range, the noise and signal distortion must be suppressed. By this way, it will indirectly increase the power consumption of analog circuits. Especially, a high-gain op-amp is necessitated to guarantee the required accuracy in the conventional pipelined ADC. However, due to the process limitations, it is difficult to implement such a high-gain op-amp. The penalty of additional power dissipation must be paid to implement this op-amp. In this thesis, a technique called as wide-band folded SHA is proposed to relax the requirement of high-gain op-amp and increase the tolerable input swing in a pipelined ADC. A 10-bit 200 MS/s pipelined ADC with the proposed wide-band folded SHA has been designed with the TSMC 0.18 �慆 CMOS 1P6M process to demonstrate the effectiveness of the proposed SHA.

Chapter Introduction……………………………………………1
1.1 Background……………………………………………………1
1.2 Motivation……………………………………………………3
1.3 Existing Methods……………………………………………3
1.4 Proposed Approaches………………………………………4
1.5 Thesis Organization………………………………………4
Chapter 2 An Introduction to Pipelined ADCs………………5
2.1 Pipelined ADC Fundamentals-Concept and Operation……5
2.2 Building Blocks in Pipelined ADC…………………………9
2.2.1 Front-End Sample and Hold Amplifier (SHA)…………9
2.2.2 Pipelined Stage……………………………………………12
2.2.2.1 Sub-ADC……………………………………………………12
2.2.2.2 Multiplying Digital to Analog Converter…………17
Chapter 3 Non-ideal Effects and Existing Performance Enhancement Techniques in Pipelined ADCs………………… 20
3.1 Non-ideal Effects and Stage Accuracy Requirement in Pipelined ADCs……………………………………………………20
3.1.1 Device Mismatch……………………………………………21
3.1.2 Finite Gain, Bandwidth and Slew Rate of Inter-Stage Amplifier……………………………………………………………23
3.1.3 Non-Zero and Signal-Dependent Switch Resistance…27
3.1.4 Electronic Noise…………………………………………29
3.2 Existing Performance Enhancement Techniques in Pipelined ADCs……………………………………………………35
3.2.1 Digital Correction and Redundancy Techniques……………………………………………………………35
3.2.2 SHA-less Architecture and Folded SHA…………………39
3.2.3 Pseudo-Differential Op-Amp and Common-Mode Stabilization Scheme………………………………………………45
Chapter 4 A 10-bit 200MS/s Pipelined ADC……………………49
4.1 Employed Design Techniques…………………………………49
4.1.1 Op-amp Sharing………………………………………………49
4.1.2 Folded SHA with Capacitor Flip-around Technique……………………………………………………………51
4.1.3 Digital Correction Circuit………………………………54
4.2 Building Blocks Design………………………………………56
4.2.1 Pseudo-differential Class-AB Gain-boosted Operational Amplifier and Integrator-based Common-mode Stabilization Technique…………………………………………56
4.2.2 Comparator……………………………………………………57
4.3 Derivation of Component Specifications…………………59
4.3.1 The Required Minimum Capacitor Size…………………59
4.3.2 Specification of the Op-amp………………………………61
4.4 Simulation Result………………………………………………63
Chapter 5 Conclusion and Future Work…………………………68
5.1 Conclusion………………………………………………………68
5.2 Future Work……………………………………………………69
Reference………………………………………………………………70

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