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研究生:黃梓期
研究生(外文):Tzu-Chi Huang
論文名稱:使用主動式電感震盪器之全數位控制式鎖相迴路
論文名稱(外文):All Digital Phase-Locked Loop Using Active Inductor Oscillator
指導教授:羅錦興羅錦興引用關係黃弘一
指導教授(外文):Ching-Hsing LuoHong-Yi Huang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:86
中文關鍵詞:鎖相迴路全數位數位控制震盪器數位控制變容器主動式電感
外文關鍵詞:digitally controlled oscillatorphase-locked loopactive inductordigitally controlled varactorall-digital
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鎖相迴路被廣泛的應用在時脈產生以及射頻電路的各種系統應用上,數位式的設計在近幾年被廣泛的研究,因為其易於變換製程、面積較小及訊號傳遞不易受雜訊影響等優點。本篇論文中提出一使用主動式電感數位控制震盪器之全數位鎖相迴路。其中使用之數位控制主動式電感提供了一較寬的輸出頻率範圍、較小晶片面積及較好的訊號品質之特性,相頻鎖定演算法配合諧振式震盪器之特性設計,去除全數位鎖相迴路中廣泛使用之時間數位轉換器並擁有好的抖動表現、精確的輸出頻率、低電路複雜度以及設計簡單之優點。全數位式鎖相迴路晶片的製作是利用台積電0.18um 1P6M之製程所製作,其操作頻率為318MHz到458MHz與鎖定時間在74個輸入週期之內。整個晶片的面積為760740 um2(中心電路:390�e390 um2),操作頻率416MHz時,其功率消耗為5.4mW。
Phase-locked loop (PLL) is a widely used circuit for clock generation and RF front-end systems. All digital designs have been researched in recent years because of the high area efficiency, adjusting to different process and low noise. In this paper, an all-digital phase-locked loop (ADPLL) using active inductor digital controlled oscillator is presented. The digital controlled active inductor offers a wide operating frequency range, good signal quality and small chip area. The novel phase lock in algorithm has the characteristics of high jitter performance, high frequency accuracy, low circuit complexity and easy design. The ADPLL implemented in a 0.18um single-poly six-metal (1P6M) technology can operate from 318MHz to 458MHz and achieve frequency acquisition within 74 reference clock cycles. The chip size is 760�e740 um2 (core: 390�e390 um2), and the power consumption is 5.4mW at 416MHz.
第一章 導論 1
1.1 研究動機與目的 1
1.2 論文組織 2
第二章 全數位式鎖相迴路先前技術探討 3
2.1 鎖相迴路種類簡介 3
2.1.1線性鎖相迴路(Linear Phase Lock Loop) 3
2.1.3全數位鎖相迴路(All Digital Phase Lock Loop) 4
2.1.4以電荷幫浦式為依據之全數位鎖相迴路(All Digital Phase Lock Loop 5
Based on a Charge Pump Phase Lock Loop Analogy) 5
2.2 電流式數位震盪器之全數位式鎖相迴路[3] 6
2.3 超快速頻率鎖定及高震盪頻率之全數位式鎖相迴路[4] 7
2.4 自動化合成時序鎖定迴路[5] 9
2.5 使用時間數位轉換器之數位式鎖相迴路[6] 11
2.6 使用時間數位轉換器及數位迴路濾波器之數位式鎖相迴路[7] 12
第三章 數位控制震盪器 14
3.1 前言 14
3.2 變容器 14
3.2.1 P-N接面變容器(P-N Junction Varactor) 14
3.2.2 NMOS變容器(NMOS Varactor) 14
3.2.3 累積型變容器(Accumulation-Mode MOS Varactor) 15
3.2.4 PMOS變容器(PMOS Varactor) 15
3.3 數位控制震盪器(Proposed DCO) 18
3.3.1 迴轉電路(Gyrator Circuit) 18
3.3.2 主動式電感壓控震盪器(Active Inductor VCO) 19
3.3.3 主動式電感數位控制震盪器(Proposed Active Inductor DCO) 21
第四章 全數位式鎖相迴路 29
4.1 全數位式鎖相迴路架構(Proposed ADPLL) 29
4.1.1 粗調與頻率擷取(Block Diagram Of The Coarse Tune And Frequency 30
Acquisition Stage) 30
4.1.2 細調與劇跳降低(Block Diagram Of The Fine Tune And Jitter 31
Reduction Stage) 31
4.2 粗調電路(Coarse Tune Circuit) 32
4.3 頻率擷取電路(Frequency Acquisition Circuit ) 33
4.4 微調電路(Fine Tune Circuit) 36
4.5 劇跳降低電路(Jitter Reduction Circuit) 41
4.6 除頻器(Divider) 41
4.7 控制電路(Control Circuit) 42
4.8 比較器(Comparator) 42
4.9 計數器(Counter) 43
4.10 相位/頻率偵測器(PFD) 43
4.11 穩定度及收斂性分析 44
4.11.1 演算法相位累積判斷及其合理範圍 45
4.11.2 演算法頻率收斂及範圍動作 48
4.11.3 收斂性結論 51
4.11.4 實際應用考量 51
4.12 設計流程 52
4.13 SPICE模擬驗證(Pre-layout simulation) 53
4.13.1 啟動狀態 53
4.13.2 粗調訊號 53
4.13.3頻率擷取訊號 54
4.13.4 微調訊號 55
4.13.5 劇跳減低訊號 55
4.13.6 整體鎖定狀態 56
4.14 結論與比較 56
第五章 晶片佈局與量測 59
5.1 晶片佈局考量 59
5.2 晶片佈局 59
5.2.1 數位震盪器佈局 60
5.2.2 記數器與比較器佈局 61
5.2.3 粗調(Coarse tune)電路佈局 62
5.2.4 頻率擷取(Frequency acquisition)電路佈局 63
5.2.5 微調(Fine tune)電路佈局 64
5.2.6 相位/頻率偵測器佈局 65
5.2.7 除頻器佈局 66
5.2.8 佈局平面圖 67
5.3 佈局後SPICE模擬驗證(Post-layout simulation) 70
5.3.1 Corner驗證 TT狀態 (Typical case) 70
5.3.2 Corner驗證 FF狀態 (Best case) 72
5.3.3 Corner驗證 SS狀態 (Worst case) 73
5.4 測試考量 75
5.5 晶片量測 78
第六章 總結與未來研究方向 83
6.1 總結 83
6.2 未來研究方向 84
References 85
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[8] Da Dalt, N., Kropf, C., Burian, M., Hartig, T. and Eul, H. “A 10b 10GHz Digitally Controlled LC Oscillator in 65nm CMOS,” in 2006 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 669–678.
[9] Sedra/Smith, Microelectronic Circuits, 5th Ed., Oxford, 2004.
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[13] TSMC 0.18um Mixed Signal 1P6M Salicide Spice Model.
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