臺灣博碩士論文加值系統

隨著半導體製程之進步，多重時脈系統單晶片的設計已經越來越普及。然而不同時脈的溝通使得系統複雜度大幅提高，矽晶片的除錯和驗證相對也變得更為困難。在本論文中我們提出一個單晶片系統除錯平台能幫助系統整合者對具有非同步溝通的系統單晶片進行完善的除錯驗證。
本論文所提出的單晶片系統除錯平台，能夠幫助系統整合者對多重時脈的系統執行硬體中斷點和單步執行除錯功能。我們分析硬體中斷點在非同步溝通上可能產生的各種問題，發展了相對應的時脈暫停技術、掃描鏈資料掃出及恢復技術和單步執行技術。我們也建立了相關的自動化軟體來簡化多重時脈系統的除錯操作流程。實驗結果顯示，藉由我們所提出之技術，使用者可很有效率地對多重時脈的系統進行除錯驗證，用以解決矽晶片除錯問題。

As more and more IP cores are integrated into a SoC, designs equipped with multiple clocks have become popular. In such designs data are frequently transferred from one clock domain to another. This cross-clock-domain data transfer feature, however, also complicates the verification and debugging processes of silicon designs. In this thesis, we present an on-chip SoC debug platform to address the multiple clock domain debug problem.
The developed debug platform provides cycle-based breakpoint insertion and single step execution capabilities. We analyze and address the potential problems induced by inserting hardware breakpoints when signals in the circuits communicate across clock domains. We also present debug techniques including clock disabling/enabling and scan dump and restore methods. A set of automation tools are also provided to reduce the required efforts to execute multi-clock debug procedures. Experimental results show that the users can efficiently employ the proposed debug platform to solve silicon debug problems in multiple clock domains.

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Overview of This Thesis 2
1.3 Organization 3
Chapter 2 Background & Previous Work 5
2.1 Background 5
2.1.1 SoC Test Platform 5
2.1.2 SoC Debug Platform 7
2.1.3 Asynchronous Error 9
2.2 Previous Work 11
2.2.1 Design for Debug in Multiple Clock Domains 12
Chapter 3 Breakpoint Insertion in Multiple Clock Domain 17
3.1 Breakpoint Insertion in Single Clock Domain 18
3.1.1 Breakpoint Setup 19
3.1.2 Gating Clock 19
3.1.3 Data Capturing & Restoring 21
3.1.4 Resuming Clock 22
3.2 Breakpoint Insertion in Multiple Clock Domain 22
3.2.1 Breakpoint Setup 22
3.2.2 Gating Clock 22
3.2.3 Data Capturing & Restoring 26
3.2.4 Resuming Clock 26
3.2.5 Hardware Breakpoint Procedure in MCD 27
Chapter 4 Implementation of SoC Debug Platform 29
4.1 The Components of Debug Platform 29
4.1.1 Hardware Components 30
4.1.2 Software Components 37
4.2 Cross Clock Domain Issues in Debug 38
4.3 Debug Mechanism of Multiple Clock Domains 40
4.3.1 Clock Control Interface 40
4.3.2 Constrained Breakpoint Insertion Mode 42
4.3.3 Selective Breakpoint Insertion Mode 44
Chapter 5 Experimental Results 47
5.1 Experimental Environment 47
5.2 Simulation Results 48
5.3 Emulation Results 52
5.3.1 Emulation Environment (FPGA Prototyping) 52
5.3.2 Graphic User Interface (GUI) 54
5.3.3 Experimental Results 55
5.4 Synthesis Results 56
Chapter 6 Conclusions and Future Work 57
6.1 Conclusions 57
6.2 Future Work 58
References 59

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