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研究生:姚奇宏
研究生(外文):Chi-Hung Yao
論文名稱:用於多重時脈系統單晶片並具有設置硬體中斷點功能之低成本除錯平台
論文名稱(外文):A Low-Cost On-Chip SOC Debug Platform with Multiple Clock Domain Breakpoint Insertion Capabilities
指導教授:李昆忠李昆忠引用關係
指導教授(外文):Kuen-Jong Lee
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:61
中文關鍵詞:除錯系統單晶片多重時脈
外文關鍵詞:debugmultiple clock domainsSoC
相關次數:
  • 被引用被引用:0
  • 點閱點閱:187
  • 評分評分:
  • 下載下載:12
  • 收藏至我的研究室書目清單書目收藏:0
隨著半導體製程之進步,多重時脈系統單晶片的設計已經越來越普及。然而不同時脈的溝通使得系統複雜度大幅提高,矽晶片的除錯和驗證相對也變得更為困難。在本論文中我們提出一個單晶片系統除錯平台能幫助系統整合者對具有非同步溝通的系統單晶片進行完善的除錯驗證。
本論文所提出的單晶片系統除錯平台,能夠幫助系統整合者對多重時脈的系統執行硬體中斷點和單步執行除錯功能。我們分析硬體中斷點在非同步溝通上可能產生的各種問題,發展了相對應的時脈暫停技術、掃描鏈資料掃出及恢復技術和單步執行技術。我們也建立了相關的自動化軟體來簡化多重時脈系統的除錯操作流程。實驗結果顯示,藉由我們所提出之技術,使用者可很有效率地對多重時脈的系統進行除錯驗證,用以解決矽晶片除錯問題。
As more and more IP cores are integrated into a SoC, designs equipped with multiple clocks have become popular. In such designs data are frequently transferred from one clock domain to another. This cross-clock-domain data transfer feature, however, also complicates the verification and debugging processes of silicon designs. In this thesis, we present an on-chip SoC debug platform to address the multiple clock domain debug problem.
The developed debug platform provides cycle-based breakpoint insertion and single step execution capabilities. We analyze and address the potential problems induced by inserting hardware breakpoints when signals in the circuits communicate across clock domains. We also present debug techniques including clock disabling/enabling and scan dump and restore methods. A set of automation tools are also provided to reduce the required efforts to execute multi-clock debug procedures. Experimental results show that the users can efficiently employ the proposed debug platform to solve silicon debug problems in multiple clock domains.
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Overview of This Thesis 2
1.3 Organization 3
Chapter 2 Background & Previous Work 5
2.1 Background 5
2.1.1 SoC Test Platform 5
2.1.2 SoC Debug Platform 7
2.1.3 Asynchronous Error 9
2.2 Previous Work 11
2.2.1 Design for Debug in Multiple Clock Domains 12
Chapter 3 Breakpoint Insertion in Multiple Clock Domain 17
3.1 Breakpoint Insertion in Single Clock Domain 18
3.1.1 Breakpoint Setup 19
3.1.2 Gating Clock 19
3.1.3 Data Capturing & Restoring 21
3.1.4 Resuming Clock 22
3.2 Breakpoint Insertion in Multiple Clock Domain 22
3.2.1 Breakpoint Setup 22
3.2.2 Gating Clock 22
3.2.3 Data Capturing & Restoring 26
3.2.4 Resuming Clock 26
3.2.5 Hardware Breakpoint Procedure in MCD 27
Chapter 4 Implementation of SoC Debug Platform 29
4.1 The Components of Debug Platform 29
4.1.1 Hardware Components 30
4.1.2 Software Components 37
4.2 Cross Clock Domain Issues in Debug 38
4.3 Debug Mechanism of Multiple Clock Domains 40
4.3.1 Clock Control Interface 40
4.3.2 Constrained Breakpoint Insertion Mode 42
4.3.3 Selective Breakpoint Insertion Mode 44
Chapter 5 Experimental Results 47
5.1 Experimental Environment 47
5.2 Simulation Results 48
5.3 Emulation Results 52
5.3.1 Emulation Environment (FPGA Prototyping) 52
5.3.2 Graphic User Interface (GUI) 54
5.3.3 Experimental Results 55
5.4 Synthesis Results 56
Chapter 6 Conclusions and Future Work 57
6.1 Conclusions 57
6.2 Future Work 58
References 59
[1]Yu-Ting Hong and Kuen-Jong Lee, “An Embedded-Processor-Driven Platform for SoC Testing,” Master Thesis, Dept. of E.E., NCKU, Taiwan, 2002

[2]B. Vermeulen, S.K. Goel, “Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips,“ ETW, pages 61-66, 2002

[3]B. Vermeulen, S.K. Goel, Tom Waayers, “Core-Based Scan Architecture for Silicon Debug,” ITC, pages 638-647, 2002

[4]Xinli Gu, Weili Wang, Kevin Li, “Re-Using DFT Logic for Functional and Silicon Debugging Test,” ITC, pages 648-656, 2002

[5]Hari Balachandran, Kenneth M, Bulter, Neil Simpson, “Facilitating Rapid First Silicon Debug,” ITC, pages 628-637, 2002

[6]By Mike Stein, Paradigm Works, “Crossing the abyss: asynchronous signals in a synchronous world,” Electronics Design, Strategy News, 2003,

[7]Cadence Design system, “Closing the Loop in Clock Domain Functional Implementation Problems,” cadence technical paper, 2004

[8]Kuen-Jong Lee, Chia-Yi Chu, and Yu-Ting Hong, “An Embedded Processor Based SoC Test Platform.” ISCAS, pages 2983-2986, 2005

[9]P. Bradley, K. Dwaeakanah, P. Levin, G. Memmi and D. Miller, “A Reconfigurable Design-for-Debug Infrastructure for SOCs.” DAC, pages 7-12, 2006

[10]Saurabh Verma, Ashima S. Dabare, Atrenta,” Understand clock domain crossing issues,” EE Times-india , 2007

[11]Wen-Cheng Huang, Chin-Yao Chang and Kuen-Jong Lee, “Toward Automatic Synthesis of SoC Test Platform,” VLSI DAT, pages 1-4, 2007

[12]Chung-Fu Kao, Ing-Jer Huang, and Chi-Hung Lin, “An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC Integration,” DAC, pages 477-482, 2007

[13]B. Vermeulen, S. Bakker, “ Debug architecture for the En-II system chip,“ IET, pages 678-684, 2007

[14]Hyunbean Yi, Snugju Park, and Sandip Kundu “A Design-for-Debug (DfD) for NoC-based SoC Debugging via NoC,” ,ATS, pages 289-294, 2008

[15]Si-Yuan Liang, “A Low-Cost On-Chip SoC Debug Platform with Hardware Breakpoint Insertion and Single Step Capabilities for IP Cores,” Master Thesis, Dept. of E.E., NCKU, Taiwan, 2008

[16]Joon-Sung Yang and Nur A. Touba ”Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture,” VTS, pages 345-351, 2008

[17]Bart Vermeulen, “Functional Debug Techniques for Embedded Systems,” IEEE D&TOC, pages 208-215,2008

[18]Liang-Bi Chen, Yung-Chih Liu, Chien-Hung Chen, Chung-Fu Kao, and Ing-Jer Huang, “Parameterized Embedded In-circuit Emulator and Its Retargetable Debugging Software for Microprocessor/Microcontroller/DSP Processor,” IEEE ASPDAC, pages 117-118, 2008

[19]Yi-Ting Lin, Wen-Chi Shiue, and Ing-Jer Huang, “A Multi-resolution AHB Bus Tracer for Real-time Compression of Forward/Backward Traces in a Circular Buffer,” DAC, pages 862-865, 2008

[20]Shan Tang and Qiang Xu, “A Debug Probe for Concurrently Debugging Multiple Embedded Cores and Inter-Core Transactions in NoC-Based Systems,” IEEE ASPDAC, pages 416-421, 2008

[21]Shan Tang, Qiang Xu, “In-band Cross-Trigger Event Transmission for Transmission for Transaction-Based Debug,” EDDA, pages 414-419, 2008

[22]ARM Ltd. Web Site, http://www.arm.com

[23]AMBA Specification, http://www.arm.com

[24]ChipScope Pro Software and Cores User Guide, Xilinx Inc.

[25]CORE Generation User Guide, Xilinx Inc

[26]IEEE 1500 Standard for Embedded Core Test (SECT), http://grouper.ieee.org/groups/1500/

[27]IEEE Computer Society, “IEEE Std. 1149.1: IEEE Standard Test Access Port and Boundary-Scan Architecture”

[28]“The Source For Perl”, http://www.perl.com/

[29]VERSATILE PLATFORM BASEBOARD User Guide, http://www.arm.com

[30]VERSATILE/LT-XC2V4000+ User Guide, http://www.arm.com
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