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研究生:蔡振宗
研究生(外文):Chen-Tsung Tsai
論文名稱:一附有回授架構並以迴轉為基礎之自我測試電路
論文名稱(外文):A Rotation-based BIST with Feedback Configurations
指導教授:李昆忠李昆忠引用關係
指導教授(外文):Kuen-Jong Lee
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:57
中文關鍵詞:測試樣本產生測試自我測試
外文關鍵詞:testingtest pattern generationbuild-in self-test
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  • 被引用被引用:0
  • 點閱點閱:123
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  • 下載下載:2
  • 收藏至我的研究室書目清單書目收藏:0
由於半導體製程迅速進步,多個電路設計常被放入至一個晶片中以完成複雜系統。這使得測試此晶片所需之測試時間拉長且增加自動化測試設備的使用。在本篇論文中,我們提出了一附有回授架構並以迴轉為基礎之自我測試電路架構去縮短測試時間及測試資料量。此架構主要的想法是利用待測電路內部的訊號去產生test seeds,這些seeds接著藉由掃描暫存器間的迴轉(rotation)來產生決定性測試樣本以及虛擬亂數測試樣本。這樣的方法可以在短時間內達到完全的錯誤涵蓋率且相較於reseeding自我測試電路,我們的架構可自行產生出所需seeds而不需儲存至ROM或是從外界傳入。除此之外,我們發展出一演算法針對提供之待測電路去決定出高效率之硬體架構以及測試流程,以達到縮短測試時間。另外,實驗結果顯示,對於ISCAS’85及ISCAS’89的標準測試電路之測試應用時間皆不超過2200以及11000個測試週期。此外,相較於先前相關成果,我們所提出的架構除了擁有原先短測試時間的優點外,100%定值錯誤涵蓋率亦是一大特點。
關鍵詞:自我測試、測試、測試樣本產生
Due to the rapid growth in semiconductor manufacturing, a large number of cores can now be plugged into a single chip. However, this also results in long test time and increases the use of ATE. In this thesis, we propose a novel mixed-mode BIST architecture, called rotation-based BIST with feedback configurations, to shorten test application time. The main idea is to make use of the logic values of the internal nodes of the circuit under test (CUT) to generate some test seeds. These seeds are then rotated in the scan registers so as to generate both deterministic and pseudo-random test patterns. With this method, full fault coverage can be achieved in a short test time. Compared to traditional reseeding-based BIST, the seeds used in our scheme can be generated on-chip and do not need to be stored in ROM or be sent from exterior. We have developed a hardware determination procedure for a provided CUT to determine the high efficient BIST architecture and its test procedure to reduce test application time. Experimental results on ISCAS’85 and ISCAS’89 benchmark circuits show that the test application time to fully test any of ISCAS’85 and ISCAS’89 benchmark circuits does not exceed 2200 and 11000 test cycles, respectively.
Key words: build-in self-test, testing, test pattern generation
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Overview 2
1.3 Organization 3
Chapter 2 Background & Previous Work 5
2.1 Background 5
2.2 Previous Work 6
Chapter 3 Rotation-Based BIST with Feedback Configurations 13
3.1 Overall Architecture 13
3.2 Feedback Mode 14
3.3 Rotation Mode 17
3.4 Test Procedure 18
3.5 Discussion 23
Chapter 4 Hardware Determination Procedure 25
4.1 Overview of Hardware Determination Procedure 25
4.2 Phase I of Hardware Determination Procedure 26
4.3 Phase II of Hardware Determination Procedure 34
Chapter 5 Experimental Results 41
5.1 The Experimental Results of Proposed Architecture 42
5.2 The Experimental Results of Area Overhead 47
5.3 Comparison with Other Works 51
Chapter 6 Conclusions & Future Work 52
6.1 Conclusions 52
6.2 Future Work 53
References 54
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