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研究生:唐興中
研究生(外文):Shing-Chung Tang
論文名稱:一種針對低複雜度低密度同位元檢查碼解碼器設計之創新記憶體配置技術
論文名稱(外文):A Novel Memory Arrangement Scheme for Low-Complexity LDPC Decoder Design
指導教授:謝明得謝明得引用關係
指導教授(外文):Ming-Der Shieh
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:99
中文關鍵詞:記憶體編組半平行解碼器低密度同位元檢查碼錯誤更正碼
外文關鍵詞:Error control codingdecoderlow-density parity-check(LDPC) codememory arrangementpartially-parallel
相關次數:
  • 被引用被引用:0
  • 點閱點閱:118
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  • 下載下載:10
  • 收藏至我的研究室書目清單書目收藏:0
低密度奇偶檢查(Low-Density Parity-Check, LDPC)碼解碼器的架構設計上,記憶體佔了解碼器大半的面積,因此若能有效的降低解碼器中的記憶體的面積,則能夠大幅改善低密度奇偶檢查解碼器的設計。為了提高解碼器之運算之平行度,傳統部分平行架構使用了許多小容量記憶體區塊,但根據一般的記憶體設計原則,在組成相同容量記憶體情況下,利用小容量記憶體區塊來組成其所佔的面積會比利用大容量記憶體區塊來的大。此外,小容量記憶體區塊功率消耗上亦會較大。基於此概念,本論文中首先提出了如何合併小容量記憶體區塊,並且提出了一套記憶體資料存取機制來解決此架構下資料存取的問題。隨後,我們提出了記憶體區塊選擇演算法,透過此演算法我們可減少記憶體群組個數及額外所付出的硬體成本。最後從實驗結果可得知,我們所提出的架構具有低複雜度與低功率消耗之優點。
Memory management plays an important role in system/component designs and it is not surprised that memory occupies a large portion of the chip area in pervasive electronic products now. In this work, we propose an efficient memory management scheme for low-density parity-check (LDPC) decoders. The aim is to reduce the total area of memory requirement in conventional partially-parallel architectures of LDPC decoders, in which a plenty of small memory blocks employed to increase the parallelism of memory access. The basic principle behind our development is from the observation that the chip area of a
memory size constructed from a set of smaller memory blocks is larger than that of the same capacity but built from a set of larger memory blocks. In addition, the former also
consumes more power than the latter according to our experiments.

This thesis explores techniques to efficiently combine small memory blocks into larger ones and proposes a FIFO-based access scheme to solve the problem of concurrent memory access in the developed architecture. Moreover, a memory blocks selection algorithm is presented to reduce the number of memory groups so that the number of additional delay elements can be minimized. Experimental results show that the proposed architecture reveals the advantages of low complexity and low power dissipation compared with the related studies.
第一章 緒論.............................................................................................................1
1.1 數位通訊系統上的錯誤控制碼................................................................1
1.2 動機..........................................................................................................3
1.3 論文大綱...................................................................................................4
第二章 研究背景......................................................................................................6
2.1 同位元檢查矩陣.......................................................................................6
2.2 LDPC編碼.................................................................................................8
2.3 LDPC解碼.................................................................................................9
2.3.1 機率域的積和演算法.......................................................................9
2.3.2 對數域的積和演算法.....................................................................17
2.4 類循環LDPC碼.....................................................................................20
2.5 部分平行的LDPC解碼器架構..............................................................23
2.5.1 檢查點運算單元.............................................................................25
2.5.2 變數點運算單元.............................................................................27
2.5.3 部分平行架構的資料運算流程.....................................................27
第三章 記憶體的組合架構與方法.........................................................................31
3.1 記憶體合併的定義.................................................................................31
3.2 記憶體儲存方式的定義..........................................................................32
3.3 檢查點運算和變數點運算階段的資料存取...........................................34
3.3.1 記憶體資料存取架構與方法.........................................................36
3.3.2 記憶體資料讀取順序.....................................................................38
3.3.3 記憶體資料寫入順序.....................................................................43
3.3.4 一般數學算式表示.........................................................................49
3.4 LDPC碼範例...........................................................................................52
第四章 記憶體單元組合方法................................................................................55
4.1 縮小相對延遲dR(Mj,k) ...........................................................................55
4.2 非列區塊合併的資料存取問題..............................................................57
4.3 記憶體編組演算法.................................................................................62
4.4 取捨分析.................................................................................................66
第五章 運算階段重疊架構....................................................................................68
5.1 運算階段重疊分析.................................................................................68
5.1.1 起始索引選取策略.........................................................................68
5.1.2 潛在的冗餘等待.............................................................................70
5.1.3 起始索引偏移方法.........................................................................71
5.2 運算階段重疊的運算單元架構..............................................................75
5.2.1 資料存取頻寬之瓶頸.....................................................................75
5.2.2 提出的運算單元架構.....................................................................75
5.2.3 運算單元之包裝介面設計.............................................................77
第六章 硬體實現與驗證........................................................................................79
6.1 硬體設計架構.........................................................................................79
6.1.1 記憶體架構....................................................................................80
6.1.2 運算單元設計................................................................................80
6.1.3 內部連線單元及資料暫存單元.....................................................82
6.1.4 終止條件檢查方法與裝置.............................................................83
6.1.5 記憶體位址產生與控制單元.........................................................84
6.2 電路驗證方法.........................................................................................85
第七章 實驗結果與比較........................................................................................87
7.1 電路實現數據.........................................................................................87
7.1.1 挑選過的欄 / 列起始索引............................................................87
7.1.2 運算階段重疊(運算單元減半).......................................................89
7.2 實現結果數據與比較..............................................................................91
第八章 結論與未來方向........................................................................................94
8.1 結論........................................................................................................94
8.2 未來方向.................................................................................................95
參考文獻.................................................................................................................97
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