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研究生:陳麒元
研究生(外文):Chi-Yuan Chen
論文名稱:基於0.18‐μmCMOS製程之遠距離音源方位估測系統單晶片設計
論文名稱(外文):System on Chip Design for Far-Field Sound Source Localization in 0.18-μm CMOS Process
指導教授:王駿發
指導教授(外文):Jhing-Fa Wang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:66
中文關鍵詞:音源定位延遲時間
外文關鍵詞:sound localizationTDOA
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  • 點閱點閱:162
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過去十幾年來,已經有非常多音源定位相關的研究被提出,但是在這些研究中,通常辨識範圍均在兩公尺以內,故我們提出了遠距離音源定位系統。音源定位的定義為,在一個有限空間內,透過發聲者與麥克風對之間的模型建立,利用延遲時間等估測的技術,我們可以對應到目前發聲者所發聲的位置。在實現上,我們可以歸納出常見的兩種實現方式。一種為利用個人電腦為平台,再透過Matlab或是其他程式語言進行模擬與實現。另一種方式為透過多媒體開發平台(DSP)實現,近來年,才開始有相關的研究實現在可規劃邏輯陣列(Field Programmable Gate Array) 或是透過特殊應用晶片Application Specific Integrated Circuit (ASIC)設計實現。
本論文提出了一個整合類比前端電路以及數位運算處理核心的系統單晶片架構,並且以台積電的0.18 μm CMOS 製程完成晶片的實現。透過矽智財的設計概念,讓我們所提出的遠距離音源辨識系統可以達到可高重複利用性、高整合性、少晶片面積,並達到低成本的特色,我們已經所提出的系統,透過Altera DEII-70 FPGA開發板完成驗證以及模擬,目前系統包含兩個主要的模組,類比前端電路則是透過國家晶片實現中心所提供的TSMC 0.18μm CMOS 1p3M+ MIM Cap 混合模製程,另外,數位訊號計算單元是利用TSMC的Artsain 0.18μm標準元件庫實現,並且透過Cadence SOC Encounter完成自動佈局及佈局後驗證。本系統在誤差角度介於±5°內,音源定位系統的辨識率可以達到90%。晶片雛型的佈局面積大小約為2.86mm × 3.56mm,平均的功率消耗約為43mW,相較於其他實現方式,我們提供了面積更小的晶片,以及更少的功率消耗。
During the past several decades, many algorithms have been proposed for sound source localization. Most of these algorithms are usually implemented by using desktop computers or digital signal processing development boards. As traditional research usually address on distance within 2 meters, we proposes a far-field sound source localization system on a chip in this thesis. The adopted method for far-field sound source localization is based on the average magnitude difference function (AMDF), and we integrate it with the voice active detection (VAD) which detects the acoustical source activity in the environment. Sound localization techniques aim to find out directions of unknown sources with a microphone array in limited space. In order to increase reusability and adaptability at system level, we present a design, which is based on the intellectual property (IP) concepts with a smaller chip size, higher integrity, and lower costs. The Analog Front End and Digital Computing Core are integrated into a chip using the TSMC 0.18-μm CMOS process. More specifically, the proposed SOC architecture for far-field sound source localization mainly consists of the following two core designs:
1. An Analog Front End module, which is designed by using TSMC 0.18μm CMOS 1p3M+ MIM Cap Mix-Mode process.
2. An Digital Computing Core, which is designed by using Artsain 0.18μm process design kit.
Finally, we evaluate the far-field sound source localization system on Altera DEII development board. The experimental results demonstrated that the proposed chip design is capable of localizing directions of sound sources. The performance can achieve 90% accuracy rate within ±5° error on average and the identifying distance can be up to 2.86mm × 3.56mm silicon area, and its average power consumption is 43mW. Compared with other systems, our solution provides a solution with a smaller area and less power consumption.
中文摘要 4
Abstract 6
CONTENTS 8
Figure List 10
Table List 12
Chapter 1 Introduction 13
1.1. Background and Motivation 13
1.2. Related Works 17
1.2.1. Subspace Based DOA Estimation Method 17
1.3. Organization of Thesis 22
Chapter 2 Overview of Time Delay of Arrival Estimation Based on AMDF 23
2.1. Generalized Correlation Method for Time Delay Estimation 23
2.2. Average Magnitude Difference Function for Time Delay Estimation 25
2.3. Method Comparison 27
Chapter 3 AMDF Based Far-Field Sound Localization System 28
3.1. Far-Field Sound Localization System Based on AMDF 28
3.1.1. Signals Model for Microphone Array 28
3.1.2. Effects of Room Reverberation 30
3.1.3. Sound Activity Detection and Energy Computing Method 32
3.1.4. Time Delay Estimation Based on Average Magnitude Difference Function (AMDF) 35
3.1.5. Sound Source Localization System based on TDOA 37
3.2. Experimental Results of Far-Field Sound Source Localization System on FPGA 43
Chapter 4 SOC Design for Far-Field Sound Source Localization 46
4.1. Proposed Architecture for Far-Field Sound Source Localization System 46
4.1.1. I/O PAD 47
4.1.2. Two-Port Memory Unit 48
4.2. A Successive Approximation Register 10 Bits Analog to Digital Converter 51
4.2.1. The Architectures of SAR ADC 51
4.3. Digital Computing Core 53
4.3.1. System Control Unit 54
4.3.2. Overview of Digital Processing Modules 55
4.4. Implementation Results of Proposed System 58
Chapter 5 Conclusions 63
References 64
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