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研究生:洪銘澤
研究生(外文):Ming-Ze Hung
論文名稱:在單晶片系統測試平台上對包覆IEEE1500之多時域待測電路進行延遲錯誤測試
論文名稱(外文):On-Chip Delay Testing for Multiple ClockDomain Cores on SoC Test Platform
指導教授:李昆忠李昆忠引用關係
指導教授(外文):Kuen-Jong Lee
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:56
中文關鍵詞:多時域單晶片延遲測試
外文關鍵詞:multiple clock domaindelay testingSoC
相關次數:
  • 被引用被引用:0
  • 點閱點閱:138
  • 評分評分:
  • 下載下載:8
  • 收藏至我的研究室書目清單書目收藏:0
隨著半導體技術的日趨進步,系統單晶片的設計整合了愈來愈多具有不同功能的核心電路以大幅降低產品成本。然而此趨勢亦提高電路之複雜度。為了有效測試一系統單晶片,通常使用的是具備大量記憶體配置、高頻率、高精準度的測試機台。但此方法將導致過高測試本。
在另外一方面,由於系統單晶片內的操作頻率愈來愈高,使得與時間延遲相關的製造缺陷逐漸成為晶片無法正確執行預定功能的主要原因之一。更且,晶片中通常會使用多個時脈供給到所含的不同電路內以達到整體晶片達到每一區塊的最高效能,使得晶片的延遲錯誤測試變得更加困難。如何利用較低成本有效達到多時域之延遲測試已成為系統單晶片技術所面臨急待解決的問題之一。
在本論文中,我們提出一項可在單晶片系統測試平台上針對已包覆IEEE 1500 標準wrapper之核心電路進行多時域延遲錯誤測試的術。所有測試訊號在晶片內部即可產生,以大幅降低外部測試機台之需求,因此只需極少測試成本。在此技術裡,我們提出一個延遲錯誤測試的時脈產生器,不僅可以觸發後擷取(launch off capture, LOC)方法在內部掃描鏈(scan chain)產生所需要的時脈訊號,亦可產生針對IEEE 1500 wrapper 所需的控制信號以及時觀察輸出響應。在實驗結果中,可看出針對多時域之延遲錯誤測試中,我們可有效地輸入測試資料至待測電路中並擷取觀察。此外,我們提出的技術所付出的硬體面積也非常的小。
Since the development of the semiconductor technology has been greatly advanced, SoC designs integrate an increasing number of cores with different functionality to reduce the total cost of products. However, the SoC-based design methodology also induces many challenges. In order to test an SoC effectively, expensive ATE with large memory, high frequency, and great accuracy is usually used. Besides, as more and more transistors with smaller size are squeezed into SoC, timing-related defects have become one of the major causes that make an SoC unfunctional. Testing the timing defects of SoC with low cost has become one of the crucial issues that need to be addressed. This thesis presents an on-chip clock generation architecture for at-speed delay test of IEEE 1500 wrapped cores. In this work, we embedded a clock generator (CG) in the IEEE 1500 test
wrapper to generate the clock pulses not only for logic belonging to single clock domain but also for crossing clock domains. Output boundary scan cells are also controlled by CG to capture fault effects from register to primary outputs. We also integrate the 1500-wrapped cores with CGs into the SoC test platform. A delay test flow is also developed. Experimental results confirm the effectiveness of the proposed on-chip clock generation architecture.
C H A P T E R 1 INTRODUCTION 1
1.1. MOTIVATION 1
1.2. OVERVIEW TO THIS WORK 2
1.3. ORGANIZATION OF THESIS 3
C H A P T E R 2 BACKGROUND AND PREVIOUS WORK 5
2.1. OVERVIEW OF DELAY FAULT MODELS 5
2.2. IEEE 1500 STANDARD 7
2.3. IEEE 1149.1 TAP CONTROLLER 9
2.4. AT-SPEED TEST METHODOLOGIES 10
2.4.1. Enhanced Scan Test (EST) 10
2.4.2. Launch Off Shift (LOS) 11
2.4.3. Launch Off Capture (LOC) 12
2.5. CLOCK DOMAINS AND CLOCK SCHEMES 14
2.6. EMBEDED PROCESSOR BASED SOC TEST PLATFORM 14
2.7. PREVIOUS WORK ON AT-SPEED TEST OF MULTIPLE CLOCK DOMAIN 18
C H A P T E R 3 ON-CHIP DELAY TESTING FOR MULTIPLE CLOCK
DOMAINS ON SOC TEST PLATFORM 25
3.1. THE HARDWARE COMPONENTS OF THE SOC TEST PLATFORM 26
3.1.1. TAM Controller 27
3.1.2. Test Bus 29
3.2. THE DESIGNS FOR AT-SPEED TESTING OF MULTIPLE CLOCK DOMAINS 30
3.2.1. Clock Generator 31
3.2.2. Output WBR Control 35
3.2.3. TAP STATE Control 38
3.2.4. TMS Generator 40
3.3. THE OVERLAP CONDITION 41
3.4. COMPARISON 42
C H A P T E R 4 EXPERIMENTAL RESULTS 44
4.1. EXPERIMENTAL ENVIRONMENT 44
4.2. TEST FLOW 46
4.3. EXPERIMENTAL RESULTS OF ON-CHIP DELAY TESTING 47
C H A P T E R 5 CONCLUSIONS AND FUTURE WORK 52
5.1. CONCLUSIONS 52
5.2. FUTURE WORK 53
REFERENCES 54
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[8] H. Yi, J. Song and S. Park, “Low-Cost Scan Test for IEEE-1500-Based SoC," Trans. on Instrumentation and Measurement, pp. 1071-1078, 2008.
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[12] M. Beck, O. Barondeau, M. Kaibel, F. Poehl, L.ub Xijiang and R. Press, “Logic Design for On-Chip Test Clock Generation-Implementation Details and Impact on Delay Test Quality,” Proc. of the Design, Automation and Test in Europe, vol. 1, pp. 56-61, 2005.
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[27] AMBA Specification, http://www.arm.com.
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