臺灣博碩士論文加值系統

在本文中，為了解決時間至數位轉換器中解析度、量測範圍以及功率消耗等關鍵規格相互牴觸之問題，提出具備高解析度及寬偵測範圍之全數位式時間數位轉換器。近代幾年所使用的轉換技術大多都以游標尺延遲線的技巧，搭配上其他技巧混合使用，可以達到數ps的解析度，但犧牲了偵測範圍或需要耗費大面積極大功率。在先前技術中，利用0.35um CMOS製程搭配類比式DLL以及暫存器達到12.2ps的高解析度以及202us的寬偵測範圍，但晶片面積達到1.3 × 1.36 mm2，而功率消耗也高達40mW；而利用0.18um CMOS製程撘配頻率至數位轉換器達到9mW及低功率的架構卻犧牲了解析度。鑒於此，提出的架構中使用游標尺延遲線以及兩組延遲鎖相迴路，利用兩組輸入參考時脈，調變及校正延遲元件的延遲時間。所提出的數位控制震盪器用了此延遲元件，因此能夠減少受到製程，溫度或電壓變化的影響。所提出的相位重疊偵測器利用三重判斷，確保了偵測的準確性；後端更利用兩組計數器來大幅度增加此架構的偵測範圍。此架構使用全數位的方式去實現，不僅有傳統架構的所有優點之外，並具有可調變的解析度，且在相同製程下得到較小的面積，較低的功率消耗。所提出的架構採用0.18um CMOS製程，輸入的參考時脈介於225MHz ~ 316MHz之間，並具有162ns的偵測範圍，以及10ps的高解析度。全數位式時間數位轉換器的晶片面積為0.806 × 0.712mm2，晶片佈局核心面積為0.309 × 0.205mm2，靜態功率消耗5.55mW，動態功率消耗為9.34mW。

In this dissertation, a high-resolution and wide-range all digital time-to-digital convertor is proposed to supply the conflicts between the key parameters such as resolution, detect range and power dissipation. In recent years, Vernier delay line technique combined with other technique are often used to achieve high resolution, but sacrificed the input range or core area. In previous techniques, using analog delay lock loop (DLL) combined with register under 0.35um CMOS process can achieve 12.2ps high resolution with 202us wide detect range, but the core area expands to 1.3 × 1.36mm2; same technique with frequency-to-digital technique under 0.18um CMOS process lower the power dissipation to 9mW, but sacrificed the resolution. The circuit utilizes a single-delay element Vernier delay line (VDL) with dual delay lock loop (DLL), combined with two reference clock to adjust and ensure the delay of the delay element. The proposed digital control oscillator formed by the delay element takes the above advantages and therefore is stabled against the variation of process, voltage and temperature (PVT). Latter phase coincidence detectors (PCD) circuits uses multiple sampling functions to detect the phase of the output signal of DCO, thus can prevent any unexpected error, and assure the accuracy of the detection. Two counters are followed as coarse and fine measurement for the circuit, so that the total detecting range can be greatly increased. Several advantages can be achieved by using all digital technique, such as higher linearity, higher resolution and faster locking speed with smaller core size.
The proposed architecture is implemented by using 0.18um CMOS process with a resolution between 10ps~80.4ps and an input range under 162ns. Reference clocks are limited between 225MHz~316MHz, due to the limited lock-in range of the DLL. The chip area is 0.806 × 0.712mm2 with the core area of 0.309 × 0.205mm2. The dynamic power dissipation is 9.34mW, and the stable power dissipation is 5.55mW.

第一章 導論 1
1.1 研究動機與目的 1
1.2 設計考量 3
1.3論文組織 4
第二章 時間數位轉換器先前技術探討 5
2.1 簡介 5
2.2 時間轉換電壓(Time-to-Voltage)之時間數位轉換器 5
2.3 雙斜率(Dual Slop)之時間數位轉換器 6
2.4 延遲線為基礎之時間數位轉換電路 7
2.5 脈衝縮減延遲元件之時間數位轉換器 8
2.6 游標尺延遲線 (Vernier Delay Line；VDL)之時間數位轉換器 10
2.7 單級游標尺元件(Single-Delay Element)之時間數位轉換器 11
2.8 兩級式時間電壓(Two-Stage Time-to-Voltage)時間數位轉換器 13
2.9 兩級式單一延遲元件時間數位轉換器 14
2.10 兩級式全數位時間數位轉換器 17
2.11 結論與結果比較 18
2.12 TDC相關技術之應用 18
第三章 全數位時間至數位轉換器 21
3.1 全數位時間數位轉換器(ADTDC)架構分析 21
3.2 全數位延遲鎖相迴路(ADDLL) 22
3.3數位控制延遲鏈(Delay Chain) 25
3.4 數位控制震盪器(Digital Control Oscillator) 27
3.5 相位重疊偵測器(Phase Coincident Detector) 29
3.6計數器(counter) 31
3.7 全數位式時間數位轉換器理論分析 32
第四章 晶片佈局與佈局後模擬 37
4.1 全數位式時間數位轉換器電路佈局 37
4.2 延遲鎖相迴路(DLL)電路佈局： 39
4.3 數位控制震盪器(Digital Control Oscillator) 41
4.4相位重疊偵測器(Phase Coincidence Detector) 42
4.5計數器(counter) 42
4.6 晶片佈局後模擬 45
4.6.1角落驗證 45
4.6.2 規格表 47
4.6.3 測試考量 48
4.7 測量結果 50
第五章 總結與未來研究方向 61
5.1 總結 61
5.2 未來研究方向 62
參考文獻 63
簡歷. 66
附錄 67

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