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研究生:林成頡
研究生(外文):Chen-Chieh Lin
論文名稱:遞迴式離散傅立葉轉換與逆修正型離散餘弦轉換之共架構設計
論文名稱(外文):A Unified Architecture Design of Recursive Discrete Fourier Transform and Inverse Modified Discrete Cosine Transform
指導教授:雷曉方
指導教授(外文):Sheau-Fang Lei
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:95
中文關鍵詞:逆修正型離散餘弦轉換傅立葉轉換免記憶體
外文關鍵詞:Memory-freeIMDCTDFT
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本篇論文提出一個基於遞迴傅立業轉換(DFT)之逆修正型離散餘弦轉換(IMDCT)共架構。可支援MP3、AAC、AAC in DRM、AC3、VQ、Ogg (N=12、36、64、128、240、256、512、1024、1920、2048、4096以及8192) 等多格式與多點數之IMDCT架構以及DFT in DRM (N=288、256、176、112)等點數。
此架構以遞迴傅立業轉換為核心架構來達到共架構之目的,配以2D演算法來提升遞迴架構速度過慢的缺點。同時,使用免記憶體式係數計算,以避免因多格式所造成之係數過多、查表法所需花費之晶片面積過大的缺點。 在硬體實現上,此一架構只需5個實數乘法器。 而所需之cycle數,與其他現有的遞迴架構文獻比較,最高可改善242倍。
本篇架構所述之電路,以TSMC 0.18μm製程實現,操作頻率為25MHz,核心面積為0.94x0.99 mm2,平均功耗22.97mW,此設計適合應用於支援多格式之多媒體系統。
The thesis presents a novel unified architecture of the recursive Discrete Fourier Transform (DFT) and the Inverse Modified Cosine Transform (IMDCT) algorithms. The proposed design is supporting multi-formats and multi-length frames, such as MP3, AAC, AAC in DRM, AC3, VQ, Ogg (N=12, 36, 64, 128, 240, 256, 512, 1024, 1920, 2048, 4096 and 8192 points) of IMDCT and DFT in DRM (N=288, 256, 176, 112 points).
In order to implement the unified architecture, the kernel of the proposed design is adpoted the recursive DFT algorithm. Due to the limit of speed of the recursive DFT architecture, we used 2-D algorithm to improve this problem. Trandicitonally, the coefficients are implemented by lookup table, but the method will cost large chip area. Thus, we use a memory-free algorithm to solve this problem. The proposed design not only reduces amounts of the coefficients greatly but also supports the multi-format for various audio codecs, if it is built in a media platform. For those of implementation, the proposed architecture only costs five multipliers. The cycle counts of the proposed architecture are 242 times improvement, and then the proposed design are lower than other existing literature of the recursive architecture.
TSMC 0.18μm CMOS 1P6M technology is used to implement the proposed design. The chip can be operated at the frequency of 25MHz, the core size
iii
is 2 0.94�e0.99mm , and the power consummation is 22.97mW. Therefore, it is more
suitable for multi-format of audio codecs.
目錄
摘要................................................. i
ABSTRACT ........................................... ii
誌謝................................................ iv
第1章- 導論 ......................................... 1
1.1. 導論............................................ 1
1.2. IMDCT架構 ...................................... 3
1.3 章節組織......................................... 5
第2章- 音訊編解碼器 ................................. 6
2.1 MP3簡介 ......................................... 6
2.2 AAC簡介 ......................................... 8
2.3 DRM簡介 ......................................... 9
2.4 AC-3簡介 ....................................... 12
2.5 TwinVQ簡介 ..................................... 13
2.6 Ogg簡介 ........................................ 15
第3章、現有遞迴IMDCT/DFT/IDFT演算法分析及實現 ...... 16
3.1 Chiang and Liu’s演算法 ........................ 16
3.2 Nikolajevic’s演算法 ........................... 20
3.2.1 Clenshaw’s 遞迴式 ........................... 20
3.2.2 MDCT 演算法起源 .............................. 21
3.2.3 IMDCT 演算法起源 ............................. 25
3.3 Chen et al. 演算法 ............................. 30
3.3.1 遞迴MDCT ..................................... 30
3.3.2 遞迴IMDCT .................................... 34
3.4 Goertzel’s 離散傅立葉轉換演算法 ............... 39
3.5 Van et al. DFT演算法 ........................... 41
第4章、係數對於晶片之影響 .......................... 48
4.1 ROM及RAM之面積及功耗 ........................... 49
4.2平行架構係數探討................................. 54
4.3 Taylor係數計算 ................................. 56
第5章、DFT/IDFT /IMDCT架構及2D演算法加速之應用 ..... 59
5.1 以DFT實現IMDCT ................................. 59
5.2 新式遞迴DFT架構 ................................ 61
5.3 2-D及管線化加速演算法 .......................... 65
5.3.1 Prime Factor 演算法 .......................... 65
5.3.2 管線化加速.................................... 66
第6章、免記憶體式係數計算 .......................... 69
6.1 單一遞迴DFT係數計算 ............................ 69
6.2 2-D遞迴DFT係數計算 ............................. 71
6.2.1 c點DFT區塊係數計算 ........................... 71
6.2.2 中間係數值區塊係數計算........................ 72
6.2.3 m點DFT區塊係數計算 ........................... 73
6.3 2-D遞迴DFT總cycles計算、統整 ................... 73
6.4 總結............................................ 75
第7章、比較分析與硬體實現 .......................... 76
7.1 所需之計算cycles數.............................. 76
7.1.1 DFT cycles數 ................................. 76
7.1.2 IMDCT cycles數 ............................... 77
7.2 計算量分析與評估................................ 79
7.3 精確度分析與評估................................ 85
7.4 硬體實現........................................ 88
第8章、未來與展望 ...................................91
參考文獻............................................ 92
參考文獻
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[21] 賴國舜, "AC-3 音訊解碼器於ARM-based平台上之軟硬體共同設計," 國立中山大學資訊工程學系,碩士論文,August 2003.
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