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研究生:歐振宇
研究生(外文):Chen-Yu Ou
論文名稱:24-GHz與60-GHzCMOS收發開關與次諧波及摺疊混頻器毫米波射頻晶片之研製
論文名稱(外文):Research on 24- and 60-GHz Millimeter-wave CMOS T/R Switches, Sub-harmonic and Folded Mixers
指導教授:莊惠如莊惠如引用關係
指導教授(外文):Huey-Ru Chuang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電腦與通信工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:87
中文關鍵詞:摺疊式混頻器收發開關次諧波混頻器
外文關鍵詞:folded mixersub-harmonic mixerT/R switch
相關次數:
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本論文研究應用於24-GHz與60-GHz接收機之CMOS射頻晶片之研製。設計的晶片包含24-GHz及60-GHz CMOS收發開關、24-GHz雙平衡式次諧波降頻混頻器與摺疊式混頻器,晶片製作均使用國家晶片中心(CIC)提供之標準TSMC CMOS 0.18 μm 製程或TSMC CMOS 0.13 μm 製程,且均使用on-wafer方式進行量測。
24-GHz收發開關的量測結果顯示之直流偏壓為1.8 V / 0 mA,消耗功率為0 mW,天線端的返回耗損為17.4 dB、接收端的返回耗損為10.8 dB、由於對稱式架構,發射端的返回耗損等同於接收端的返回耗損為10 .8 dB、插入損失為6.0 dB、發射模式時發射端與接收端之間的隔離度為32.4 dB、接收模式時天線端與發射端之間的隔離度為25.8 dB、input P1dB為21.5 dBm、IIP3為32.6 dBm。60-GHz收發開關的量測結果顯示電路之直流偏壓為1.2 V / 0 mA,消耗功率為0 mW,天線端的返回耗損為14.6 dB、接收端的返回耗損為8.4 dB、由於對稱式架構,發射端的返回耗損等同於接收端的返回耗損為8.4 dB、插入損失為11.2 dB、發射模式時發射端與接收端之間的隔離度為34.4 dB、接收模式時天線端與發射端之間的隔離度為21.5 dB、input P1dB為9.5 dBm。
24-GHz次諧波混頻器量測結果顯示混頻器核心電路之直流偏壓為1.5 V / 2.08 mA,消耗功率為3.12 mW,輸出主動平衡器與緩衝放大器之直流偏壓為1.8 V / 7 mA,消耗功率為12.6 mW。RF端輸入的返回耗損大於8 dB、LO端輸入的返回耗損大於10 dB、IF端輸出的返回耗損大於10 dB、轉換增益為4.01 dB、input P1dB為-12.5 dBm、IIP3為-3.25 dBm、LO-RF隔離度為38 dB,LO-IF隔離度為40 dB、RF-IF隔離度為40.5 dB、2LO-RF隔離度為65.5 dB與2LO-IF隔離度為70 dB。
24-GHz摺疊式混頻器模擬結果顯示混頻器核心電路之直流偏壓為1 V / 12 mA,消耗功率為12 mW,緩衝放大器之直流偏壓為1 V / 10 mA,消耗功率為10 mW。RF端輸入匹配大於10 dB、IF端輸出的返回耗損大於10 dB、轉換增益為-0.5 dB、input P1dB為-6 dBm、LO-RF隔離度為43.8 dB,LO-IF隔離度為45 dB、RF-IF隔離度為41.2 dB。
This thesis presents the design of Millimeter-wave CMOS T/R switches, sub-harmonic and folded mixers. The designed CMOS RFICs are fabricated with TSMC CMOS 0.18 μm 1P6M and TSMC 0.13 μm 1P8M standard process. The design of a 24-GHz CMOS T/R switch combines the shunt inductor resonance and body-floating schemes. The T/R switch exhibits a high isolation and good linearity performance. The design of a 24-GHz sub-harmonic mixer and a 24-GHz folded mixer are also presented.
第一章 緒論 1
1.1 無證照通訊頻帶之研究背景 1
1.2 無線通訊60-GHz WPAN 發展技術與系統簡介 2
1.2.1 毫米波簡介 2
1.2.2 實驗室60-GHz WPAN系統規劃 4
1.3 24-GHz汽車雷達及ISM band(24-24.25 GHz)應用 5
1.4 論文架構 7
第二章 24-GHz及60-GHz CMOS射頻收發開關 (TSMC 0.18 μm、TSMC 0.13 μm) 9
2.1 收發開關運作原理與重要參數介紹 9
2.1.1 PIN Diode switch 10
2.1.2 GaAs MESFET switch 11
2.1.3 CMOS switch 12
2.2 電晶體開關模型分析 13
2.2.1 電晶體小訊號模型 13
2.2.2 電晶體大訊號模型 16
2.3 高隔離度與高線性度之設計 17
2.3.1 並聯電感諧振技術 17
2.3.2 Body-floating技術 18
2.4 24-GHz CMOS射頻收發開關之設計 20
2.4.1 串聯電晶體大小設計 20
2.4.2 並聯電晶體大小設計 22
2.4.3 加入並聯電感諧振技術 23
2.4.4 加入body-floating技術 24
2.4.5 TSMC 0.18 μm電磁模擬環境驗證 25
2.4.6 完整電路設計與佈局考量 26
2.4.7 模擬與量測結果 28
2.5 60-GHz CMOS射頻收發開關之設計 32
2.5.1 完整電路設計與考量 32
2.5.2 模擬與量測結果 35
2.6 結果與討論 39
2.6.1 24-GHz CMOS 射頻收發開關結果與討論 39
2.6.2 60-GHz CMOS 射頻收發開關結果與討論 39
第三章 24-GHz雙平衡式次諧波降頻混頻器 (TSMC 0.18 μm) 41
3.1 混頻器原理與重要參數介紹 41
3.2 各式混頻器架構介紹 43
3.2.1 電阻性混頻器 44
3.2.2 平方律混頻器 45
3.2.3 吉伯特混頻器 46
3.3 24-GHz次諧波混頻器之設計 49
3.3.1 次諧波混頻器混頻原理 50
3.3.2 次諧波混頻器架構 51
3.3.3 24-GHz次諧波混頻器之實現 53
3.3.4 完整電路設計與佈局考量 61
3.3.5 模擬與量測結果 62
3.4 結果與討論 68
第四章 24-GHz雙平衡摺疊式降頻混頻器 (TSMC 0.13 μm) 69
4.1 摺疊式混頻器原理 69
4.2 24-GHz摺疊式混頻器之實現 71
4.3 完整電路設計與佈局考量 76
4.4 模擬與量測結果 77
4.5 結果與討論 82
參 考 文 獻 85
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