臺灣博碩士論文加值系統

在本論文中，對於光罩佈局中的整合電路，我們提出一個針對短路錯誤的計算關鍵區域的方法。這個方法是利用取樣架構與關鍵區域的幾何計算的概念。藉由建立一個記錄密度表，我們加權的取樣方法可以讓結果更為準確且更適合較大的設計。這個演算法被建立在一個開放存取的平台上並且可以有效地從任意的佈局中萃取出關鍵區域。結果顯示，這個方法可以降低計算成本；同時，也可以保持準確性。

In this thesis, we present a method of computing critical area for short faults of an integrated circuit from the mask layout. The method is based on the concept of sampling
framework and the geometry computation of critical area. By constructing the density table of layout, our weighted sampling approach can be more accurate and more suitable for the larger device. The algorithm has been implemented within OpenAccess platform to allow efficient extraction of the critical area from an arbitrary mask layout. The results
show that this method can reduce computation cost; meanwhile, it can maintain the accuracy.

書頁名 i
授權書 ii
論文口試委員審書 iii
中文摘要 iv
英文摘要 v
誌謝 vi
目錄 vii
表目錄 ix
圖目錄 x
1 Introduction 1
1.1 Our Contribution 2
1.2 Thesis Organization 2
2 Preliminary 3
2.1 Critical Area and Yield Models 3
2.2 Previous Works 4
2.2.1 Geometric Method 5
2.2.2 Monte Carlo Method 5
2.2.3 Stochastic Method 6
2.3 OpenAccess : Modern EDA Database Adoption 7
2.4 Problem Formulation 8
3 Algorithm 10
3.1 Data Translation and Transformation 10
3.2 Density Table Generation 13
3.3 Sampling Framework . . 15
3.3.1 Weighted Sampling . . . 15
3.3.2 Shape Expansion 17
3.3.3 Polygon Clipping 17
3.4 Critical Area Estimation 21
4 Experimental Results . 23
5 Conclusions and Future Works 26
參考文獻. 27
自傳. . . 30

[1] Silicon Integration Initiative. Inc. “Si2 OpenAccess API Tutorial”.
[2] T. Asami, H. Nasu, H. Takase, H. Oyamatsu, and M. Tsutsui. “Advanced yield enhancement methodology for SoCs”. Proceedings of IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, pages 144–147, May
2004.
[3] F. Lee, A. Ikeuchi, Y. Tsukiboshi, and T. Ban. “Critical Area Optimizations Improve IC Yields”. EETimes, Jan 2006.
[4] W. Kuo and T. Kim. “An Overview of Manufacturing Yield and Reliability Modeling for Semiconductor Products”. Proceedings of the IEEE, pages 1329–1344, Aug 1999.
[5] G. A. Allan. “A Comparison of Efficient Dot Throwing and Shape Shifting Extra Material Critical Area Estimation”. Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pages 44–52, 1998.
[6] H. Xue, C. Di, and J.A.G. Jess. “Fast Multi-Layer Critical Area Computation”. Proceedings of IEEE Workshop on Defect and Fault Tolerance in VLSI Systems, pages 117–124, Oct 1993.
[7] H. Xue, C. Di, and J.A.G. Jess. “A Net-Oriented Method for Realistic Fault Analysis”. Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pages 78–83, Nov 1993.
[8] D. N. Maynard adn J. D. Hibbeler. “Measurement and Reduction of Critical Area using Voronoi Diagrams”. Proceedings of IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, pages 243–249, April 2005.
[9] D. Lee and E. Papadopoulou. “Critical Area Computation - A New Approach”. Proceedings of ISPD, pages 89–94, April 1998.
[10] J. Segal, S. Bakarian, and R. Ross. “Impact of Simulation Parameters on Critical Area Analysis”. Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pages 14–19, Nov 1999.
[11] Inc. Ponte Solutions. “White Papers : Understanding Design For Yield”. Mentor Graphics, 2006.
[12] P. Zarkesh-Ha and K. Doniger. “Stochastic interconnect layout sensitivity model”. Proceedings of International Workshop on System Level Interconnect Prediction, March 2007.
[13] G. A. Allan. “Yield Prediction by Sampling IC Layout”. Proceedings of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pages 359–371, MAR 2000.
[14] M. Guiney and E. Leavitt. “An Introduction To OpenAccess An Open Source Data Model and API for IC esign ”. Proceedings of IEEE Asia and South Pacific Conference on Design Automation, pages 434– 436, Jan 2006.
[15] K. Weiler and P. Atherton. “Hidden Surface Removal Using Polygon Area Sorting ”. Proceedings of the 4th Annual Conf. on Computer Graphics and Interactive Techniques, pages 214–222, 1977.
[16] S.K. Sharif, P. Sagar, and A. Markosian. “Enhancing Defect limited Yield using Astro/ICC Advanced Features”. EDACafe, Sep 2006.
[17] G. A. Allan and A. J. Walton. “Hierarchical Critical Area Extraction with the EYE tool”. Proceedings of IEEE Workshop on Defect and Fault Tolerance in VLSI Systems, pages 28–36, Nov 1995.
[18] J. H. N. Mattick, R. W. Kelsall, and R. E. Miles. “Reliability Prediction through Critical Area Analysis”. Proceedings of IEEE Integrated Reliability Workshop, page 167, Oct 1995.
[19] O. Rizzo and H. Melzner. “Concurrent Wire Spreading, Widening, and Filling”. Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pages 350–353, June 2007.
[20] J. T. Yan and B. Y. Chiang. “Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area”. Proceedings of IEEE VLSI Design International Conference on Embedded Systems, pages 899–906, Jan 2007.
[21] G. J. Gaston and G. A. Allan. “Yield Prediction using Calibrated Critical Area Modelling”. Proceedings of IEEE International Conference on Microelectronic Test Structures, pages 7–10, Mar 1997.
[22] G. A. Allan and A. J. Walton. “Efficient Extra Material Critical Area Al-
gorithms”. Proceedings of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18:1480–1486, Oct 1999.