跳到主要內容

臺灣博碩士論文加值系統

(44.201.94.236) 您好!臺灣時間:2023/03/25 00:11
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:史汝敏
研究生(外文):JuMin Shih
論文名稱:高速序列傳輸之內建自我測試電路設計
論文名稱(外文):High Speed Serial Link Built-in Self Test Circuit Design
指導教授:蘇朝琴
指導教授(外文):ChauChin Su
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電機學院IC設計產業專班
學門:商業及管理學門
學類:其他商業及管理學類
論文種類:學術論文
論文出版年:2008
畢業學年度:97
語文別:中文
論文頁數:91
中文關鍵詞:數位控制延遲電路數位/類比訊號轉換器高速序列傳輸眼圖遮罩內建自我測試
外文關鍵詞:digital control delay linedigital-to-analog converterhigh speed serial linkeye maskbuilt-in self test
相關次數:
  • 被引用被引用:0
  • 點閱點閱:317
  • 評分評分:
  • 下載下載:78
  • 收藏至我的研究室書目清單書目收藏:0
本論文提出一個高速序列傳輸之內建自我測試電路設計 (High Speed Serial Link Built-in Self Test Circuit Design) 電路,用來降低生產測試成本。利用數位控制延遲電路 (Digital Control Delay Line:DCDL) 產生特定相位之時脈,取樣並保持電路 (Sample and Hold:S/H) 抓取輸入的眼圖 (Eye Diagram) 訊號,與數位/類比訊號轉換器 (Digital-to-Analog Converter:DAC) 輸出的某特定電壓做比較,判斷眼圖有無張開至特定規格,由於不需要高速的測試儀器,可大幅降低測試成本。
高速序列傳輸之內建自我測試電路設計將至聯華電子股份有限公司 (United Microelectronics Corporation:UMC) 下線,所使用製程是 UMC 90nm 1P9M Logic / Mixed Mode Low-K SP-RVT Process 來實現。眼圖之抖動解析度為2.8ps,眼圖之振幅解析度為4.68mV,眼圖之振幅量測範圍為0~1.2V,完成眼圖之總量測時間為655G位元時間,核心電路的面積為270μm2 X 171μm2,模擬眼圖皆達到我們所預期的行為。
In this thesis, we propose a high speed serial link built-in self test circuit design for low-cost mass production. It includes a Digital Control Delay Line (DCDL) for clock delay adjustment, a Sample and Hold (S/H) module for capture the signal, a Digital-to-Analog Converter (DAC) to set up the compared level. Because it does not need high-speed tester, the test can be reduced significantly.
The proposal high speed serial link built-in self test circuit is designed in an UMC 90nm 1P9M Logic / Mixed Mode Low-K SP-RVT Process. The jitter resolution for the eye diagram measurement is 2.8ps. The amplitude resolution is 4.68mV, and the amplitude range is ±600mV. The chip occupies a core area of 270μm2 X 171μm2, the post-simulation eyes diagram all reaches our anticipated behavior.
摘 要 ............I
ABSTRACT II
目 次 ......... III
表 次 ..........V
圖 次 .........VI
致 謝 .........IX
第1 章 介紹 .................1
1-1 研究動機 ................1
1-2 設計流程 ................3
1-3 論文組織 ................5
第2 章 電路設計 .............7
2-1 系統行為 ..............7
2-2 區塊電路規格 ....10
2-3 區塊電路 ............11
2-3-1 取樣並保持電路 ........11
2-3-2 數位/類比訊號轉換器 ...14
2-3-3 數位控制延遲電路 ......26
2-3-4 比較器 ..............45
2-3-5 計數器 ..............53
第3 章 系統 ....................61
3-1 系統運作 ..............61
3-2 模擬結果 ..............66
3-3 佈局 ..................68
3-4 腳位功能描述 ......75
第4 章 測試環境 ..........78
4-1 測試環境 ..............78
4-2 測試流程 ..............79
4-3 測試項目 ..............81
4-3-1 基本功能測試模式 ......81
4-3-2 區塊測試模式 ..83
4-3-3 眼圖張開測試模式 ....................84
第5 章 結論 ....................85
參考資料 ...89
[1]PCI-SIG, “PCI Express Base Specification Revision 2.0a,” December 20, 2006.
[2]PCI-SIG, “PCI Express Architecture PCI Express™ Jitter and BER Revision 1.0,” February 11,2005
[3]A. H. Chan and G. W. Roberts, "A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line," itc, pp.858-867, International Test Conference 2001 (ITC'01), 2001
[4]A. H. Chan and G. W. Roberts, "A deep sub-micron timing measurement circuit using a single-stage vernier delay line," Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002 , pp. 77-80, 2002
[5]N. Abaskharoun, M. Hafed and G. W. Roberts, "Strategies for on-chip sub-nanosecond signal capture and timing measurements," Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on , vol.4, no., pp.174-177 vol. 4, 6-9 May 2001
[6]T. Xia, H. Zheng, J. Li and A. Ginawi, "Self-refereed on-chip jitter measurement circuit using Vernier oscillators," VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on , vol., no., pp. 218-223, 11-12 May 2005
[7]K. H. Cheng, S. Y. Jiang and Z. S. Chen, "BIST for clock jitter measurements," Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on , vol.5, no., pp. V-577-V-580 vol.5, 25-28 May 2003
[8]V. Gutnik and A. Chandrakasan, "On-chip picosecond time measurement," VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on , vol., no., pp.52-53, 2000
[9]C. C. Tsai and C. L. Lee, "An on-chip jitter measurement circuit for the PLL," Test Symposium, 2003. ATS 2003. 12th Asian , vol., no., pp. 332-335, 16-19 Nov. 2003
[10]J. J. Huang and J. L. Huang, "A low-cost jitter measurement technique for BIST applications," ats, pp. 336-339, 12th Asian Test Symposium (ATS'03), 2003
[11]J. J. Huang and J. L. Huang, "An infrastructure IP for on-chip clock jitter measurement," Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on , vol., no., pp. 186-191, 11-13 Oct. 2004
[12]B. Nelson and M. Soma, "On-chip calibration technique for delay line based BIST jitter measurement," Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on , vol.1, no., pp. I-944-7 Vol.1, 23-26 May 2004
[13]S. Sunter and A. Roy, "BIST for phase-locked loops in digital applications," itc, pp.532-540, International Test Conference 1999 (ITC'99), 1999
[14]T. J. Yamaguchi and M. Ishida, et al., "A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals," vts, pp.102-110, 19th IEEE VLSI Test Symposium, 2001
[15]H. C. Lin and K. Taylor, et al., "CMOS built-in test architecture for high-speed jitter measurement," itc, pp. 67-76, International Test Conference 2003 (ITC'03), 2003
[16]K. Taylor and B. Nelson, et al., "Experimental Results for High-Speed Jitter Measurement Technique," itc, pp. 85-94, 26-28, International Test Conference 2004 (ITC'04), 2004
[17]K. A. Taylor and B. Nelson, et al., "Special issue on BIT CMOS built-in test architecture for high-speed jitter measurement," Instrumentation and Measurement, IEEE Transactions on , vol.54, no.3, pp. 975-987, June 2005
[18]K. H. Cheng and S. Y. Jiang, "High accuracy jitter measurement using cyclic pulse width modulation structure," VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on , vol., no., pp. 24-27, 27-29 April 2005
[19]J. M. Cazeaux, M. Omana and C. Metra, "Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop," iolts, pp. 17-22, International On-Line Testing Symposium, 10th IEEE (IOLTS'04), 2004
[20]C. F. Li, S. S. Yang and T. Y. Chang, "On-chip accumulated jitter measurement for phase-locked loops," Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific , vol.2, no., pp. 1184-1187 Vol. 2, 18-21 Jan. 2005
[21]M. Ishida and K. Ichiyama, et al., "A programmable on-chip picosecond jitter-measurement circuit without a reference-clock input," Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International , vol., no., pp.512-614 Vol. 1, 10-10 Feb. 2005
[22]T. Xia and J. C. Lo, "Time-to-voltage converter for on-chip jitter measurement," Instrumentation and Measurement, IEEE Transactions on , vol.52, no.6, pp. 1738-1748, Dec. 2003
[23]T. Xia and J. C. Lo, "On-chip jitter measurement for phase locked loops," Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. 17th IEEE International Symposium on , vol., no., pp. 399-407, 2002
[24]K. A. Jenkins, A. P. Jose and D.F. Heidel, "An on-chip jitter measurement circuit with sub-picosecond resolution," Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European , vol., no., pp. 157-160, 12-16 Sept. 2005
[25]B. Analui, A. Rylyakov, S. Rylov, M. Meghelli and A. Hajimiri, "A 10-Gb/s two-dimensional eye-opening monitor in 0.13-/spl mu/m standard CMOS," Solid-State Circuits, IEEE Journal of , vol.40, no.12, pp. 2689-2699, Dec. 2005
[26]T. A. Lindsay, "Innovations in BER testers enable fast and accurate eye diagram, eye mask, Q-factor, and jitter measurements," Optical Fiber Communication Conference, 2004. OFC 2004 , vol.2, no., pp. 4 pp. vol.2-, 23-27 Feb. 2004
[27]A. Amerasekera and C. Duvvury, "ESD in silicon integrated circuits", USA; John Wiley & Sons,Ltd,2002:326-344.
[28]N. Abaskharoun and G. W. Roberts, "Circuits for on-chip sub-nanosecond signal capture and characterization," Custom Integrated Circuits, 2001, IEEE Conference on. , vol., no., pp.251-254, 2001
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top