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研究生:魏仕勳
論文名稱:維特比解碼器於PACDSP平台之實作設計
論文名稱(外文):The Implementation of Viterbi Decoder on PACDSP Platform
指導教授:陳紹基陳紹基引用關係
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電機學院IC設計產業專班
學門:商業及管理學門
學類:其他商業及管理學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:100
中文關鍵詞:維特比解碼器數位信號處理器
外文關鍵詞:Viterbi DecoderDSPPACDSP
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PACDSP為一個本國製且有效率之數位信號處理器平台,特別適合多媒體應用,在可取得之文獻中,僅有少部份有關通訊系統之應用實現於PACDSP平台上,本論文率先將維特比解碼器實作於PACDSP平台。維特比解碼器是通訊系統接收機內耗費最多資源的運算之一,因此,為了減少其在PACDSP平台上之運算時脈數,本論文採用了VLIW及SIMD架構,並針對記憶體及暫存器的使用進行良好的配置,實作一個數位系統廣播系統規格之高平行度軟判決維特比解碼器,本設計可在操作頻率為200MHz之運算速度下,每一個叢集可達到1Mbps之資料解碼速度。此外,本論文亦針對PACDSP平台實作通訊系統進行效率評估,並建議在PACDSP平台新增若干新特殊指令,以增進其運算效能。
PACDSP is an efficient native DSP processor suitable for multimedia applications. For telecommunication applications, little work has been done for their realizations on PACDSP in literature. This work is the first one to implement the Viterbi decoder on PACDSP. A Viterbi decoder consumes significant amount of resource in a receiver. Hence, for reducing the execution cycles on PACDSP, this work utilizes the techniques of VLIW, SIMD, memory collocation, and register allocation to implement a highly-parallel soft-decision Viterbi decoder for DVB system. This design can execute up to 1Mbps output data rate per cluster with operating frequency of 200MHz. Furthermore, this work also evaluates the efficiency of PACDSP in implementing communication systems, and suggests several new special instructions for PACDSP platform to enhance its executing performance.
第一章 緒論 1
1.1 研究背景與動機 1
1.2 論文架構 4

第二章 DVB系統之Viterbi Decoder 5
2.1 Convolutional code 5
2.2 Viterbi演算法 8
2.3 DVB系統 13
2.3.1 系統概要 13
2.3.2 DVB-T 系統之傳送機架構 15
2.3.3 DVB-T 系統之內編碼器 19
2.3.4 DVB-T 系統之接收機架構 21
2.4 利用DSP平台實作之DVB-T系統接收機及Viterbi Decoder 25
2.4.1 利用DSP平台實作之DVB-T系統接收機 25
2.4.2 利用DSP平台實作之Viterbi Decoder 27

第三章 PACDSP概觀 30
3.1 簡介 30
3.2 架構 32
3.2.1 PACDSP架構 32
3.2.2 Program Sequence Control Unit 33
3.2.3 Scalar Unit 33
3.2.4 VLIW Datapath 34
3.2.5 客製化功能單元 36
3.2.6 記憶體介面 37
3.3 暫存器組織 38
3.3.1 Scalar Unit暫存器組織 39
3.3.2 VLIW Datapath暫存器組織 40
3.4 指令集架構及管線層級 43
3.4.1 指令集架構 43
3.4.2 管線層級 44
3.5 電力模式 45
3.6 PACDSP 組合語言設計簡介 46
3.6.1 指令封包 46
3.6.2 指令格式 47
3.6.3 資料傳遞 48
3.6.4 位址模式 50
3.7 PACDSP 軟體發展工具 51
3.8 PACDSP 新平台 52
3.8.1 PAC-plus!及Dual-Core PAC SoC (PAC solo) 53
3.8.2 PAC II 53

第四章 實作Viterbi Decoder於PACDSP平台 55
4.1 於PACDSP平台實作之Viterbi Decoder架構 55
4.1.1 BMU 56
4.1.2 ACSU 57
4.1.3 SMU 58
4.1.4 MATLAB 模擬結果 59
4.2 以組合語言於PACDSP平台實作之Viterbi Decoder 63
4.2.1 解碼流程 64
4.2.2 BMU之組合語言設計 66
4.2.3 ACSU之組合語言設計 67
4.2.4 SMU之組合語言設計 69
4.2.5 兩種資料平行處理模式 70
4.2.6 最佳化技巧 70
4.3 實作結果 72
4.3.1 ISS模擬結果 72
4.3.2 記憶體需求 73
4.4 針對PACDSP平台實作通訊系統之效能分析 75

第五章 PACDSP 特殊指令建議 77
5.1針對Viterbi Decoder提出之特殊指令 77
5.1.1 特殊指令 ACS 78
5.1.2 特殊指令 TB 81
5.2針對Data Transfer提出之特殊指令 82
5.2.1 特殊指令 UNPW、UNPHW、PW、PHW 83
5.2.2 特殊指令 SWAP4R 86
5.2.3 特殊指令 EXTRACTAI 87
5.3 特殊指令評估 88

第六章 結論 90

參考文獻 92

附錄A 97
A.1 BMU之組合語言關鍵部分 97
A.2 ACSU之組合語言關鍵部分 98
A.3 SMU之組合語言關鍵部分 99
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