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研究生:林俊瑋
研究生(外文):Lin, Jyun-Wei
論文名稱:以硬體協助之多核心嵌入式系統效能與耗能評估工具
論文名稱(外文):Hardware-Assisted Performance/Energy Evaluation Tool for Multi-core Embedded System
指導教授:曹孝櫟曹孝櫟引用關係
指導教授(外文):Tsao, Shiao-Li
學位類別:碩士
校院名稱:國立交通大學
系所名稱:資訊科學與工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:34
中文關鍵詞:多核心嵌入式系統效能耗能評估工具
外文關鍵詞:Multi-coreEmbedded SystemPerformanceEnergy ConsumptionEvaluation Tool
相關次數:
  • 被引用被引用:0
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  • 下載下載:34
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有效的效能與耗能評估是嵌入式系統設計時期的關鍵技術。然而,傳統的評估方法難以兼具快速以及精確。此外在多核心逐漸應用於嵌入式系統的今日,傳統的評估方法將面臨更為複雜及困難的挑戰。有鑑於此,本文提出一種以硬體協助且適用於多核心嵌入式系統的效能與耗能評估工具,並予以實現。所提之工具提供程式執行時期硬體事件的監控,並藉此推算出元件耗能,其可避免軟體取樣(Sampling)所造成的額外負擔,以便能呈現系統原始的行為與特性。實驗結果顯示,所提之方法可於100 MHz的四核心仿真環境下進行,精度可達微秒以下,其兼具快速、精細且真實的特性將有助於複雜多核心嵌入式系統設計時期之細部評估與分析。
Effective performance and energy evaluation of embedded systems is one of the critical issues during design phase. However, conventional approaches suffer from difficulties to provide fast and accurate evaluation of the system, especially for those embedded systems using multi-core technology. In this thesis, we propose and realize a hardware-assisted performance and energy evaluation tool for a multi-core embedded system. Our approach provides hardware monitor for runtime programs, and uses these monitor information to estimate the system energy consumption without introducing extra software sampling overhead. The experimental results show that our approach can work at a 100 MHz quad-core emulation platform. The profiling granularity is higher than microsecond. It provides fast and fine-grained evaluation of the multi-core embedded system during the design phase.
摘要 i
Abstract ii
誌謝 iii
Contents iv
List of Tables v
List of Figures vi
Chapter 1. Introduction 1
Chapter 2. Related Work 3
2.1. Performance Evaluation 3
2.1.1. Software Simulation 3
2.1.2. Software Profiling 4
2.1.3. Runtime Hardware Monitor 6
2.2. Energy Evaluation 8
2.2.1. Circuit Simulation 8
2.2.2. Hardware Measurement 8
2.2.3. Architecture-Level Evaluation 8
Chapter 3. Performance/Energy Evaluation Tool for Multi-core Embedded Systems 11
3.1. Performance and Energy Evaluation Methodology 12
3.2. Proposed Evaluation Architecture 13
3.3. Energy Model 15
3.4. Advantages of Our Approach 17
Chapter 4. Implementation 18
4.1. Emulation Platform 19
4.1.1. GRLIB Open Source IP Library 19
4.1.2. LEON3 MPSoC Emulation Environment 20
4.1.3. DE3 Development and Education Board 21
4.1.4. SnapGear Embedded Linux Distribution for LEON3 21
4.2. Evaluation of LEON3 Processor 23
4.2.1. Runtime Performance Monitor 23
4.2.2. Energy Calculation 24
Chapter 5. Experimental Results 26
5.1. Case Study: SPLASH-2 FFT 29
Chapter 6. Conclusions 31
References 32
[1] NVIDIA Tegra.
http://www.nvidia.com/page/handheld.html
[2] Qualcomm Snapdragon.
http://www.qctconnect.com/products/snapdragon.html
[3] Texas Instruments OMAP 4 Platform.
http://www.ti.com/omap4_platform
[4] ARM11 MPCore.
http://www.arm.com/products/CPUs/ARM11MPCoreMultiprocessor.html
[5] L. Shannon and P. Chow, “Using Reconfigurability to Achieve Real-Time Profiling for Hardware/Software Codesign,” Proceedings of the 12th International Symposium on Field Programmable Gate Arrays, pp. 190-199, Monterey, California, February 2004.
[6] J. G. Tong and M. A. S. Khalid, “Profiling Tools for FPGA-Based Embedded Systems: Survey and Quantitative Comparison,” Journal of Computers, Vol. 3, No. 6, pp. 1-14, June 2008.
[7] A. Bhattacharjee, G. Contreras, and M. Martonosi, “Full-System Chip Multiprocessor Power Evaluations Using FPGA-Based Emulation,” Proceedings of the 13th International Symposium on Low Power Electronics and Design, pp. 335-340, Bangalore, India, August 2008.
[8] M. A. Ghodrat, K. Lahiri, and A. Raghunathan, “Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation,” Proceedings of the 44th Design Automation Conference, pp. 883-886, San Diego, California, June 2007.
[9] T. Austin, E. Larson, and D. Ernst, “SimpleScalar: An Infrastructure for Computer System Modeling,” IEEE Computer, Vol. 35, No. 2, pp. 59-67, February 2002.
[10] CoWare Platform Architect.
http://www.coware.com/products/platformarchitect.php
[11] M. M. K. Martin, D. J. Sorin, B. M. Beckmann, M. R. Marty, M. Xu, A. R. Alameldeen, K. E. Moore, M. D. Hill, and D. A. Wood, “Multifacet's General Execution-driven Multiprocessor Simulator (GEMS) Toolset,” ACM SIGARCH Computer Architecture News, Vol. 33, No. 4, pp. 92-99, November 2005.
[12] N. L. Binkert, R. G. Dreslinski, L. R. Hsu, K. T. Lim, A. G. Saidi, and S. K. Reinhardt, “The M5 Simulator: Modeling Networked Systems,” IEEE Micro, Vol. 26, No. 4, pp. 52-60, July 2006.
[13] J. Renau, B. Fraguela, J. Tuck, W. Liu, M. Prvulovic, L. Ceze, S. Sarangi, P. Sack, K. Strauss, and P. Montesinos, SESC: Cycle Accurate Architectural Simulator, January 2005.
http://sesc.sourceforge.net
[14] L. Benini, D. Bertozzi, A. Bogliolo, F. Menichelli, and M. Olivieri, “MPARM: Exploring the Multi-Processor SoC Design Space with SystemC,” Journal of VLSI Signal Processing, Vol. 41, No. 2, pp. 169-182, September 2005.
[15] J. Cong, K. Gururaj, G. Han, A. Kaplan, M. Naik, and G. Reinman, “MC-Sim: An Efficient Simulation Tool for MPSoC Designs,” Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, pp. 364-371, November 2008.
[16] Intel VTune Performance Analyzer.
http://www.intel.com/cd/software/products/asmo-na/eng/vtune/239144.htm
[17] OProfile - A System Profiler for Linux.
http://oprofile.sourceforge.net
[18] GNU gprof.
http://www.cs.utah.edu/dept/old/texinfo/as/gprof.html
[19] ARM11 MPCore Processor Technical Reference Manual, ARM Limited, 2008.
[20] S. Browne, J. Dongarra, N. Garner, G. Ho, and P. Mucci, “A Portable Programming Interface for Performance Evaluation on Modern Processors,” International Journal of High Performance Computing Applications, Vol. 14, No. 3, pp. 189-204, April 2000.
[21] M. E. Shobaki and L. Lindh, “A Hardware and Software Monitor for High-Level System-on-Chip Verification,” Proceedings of the 2nd International Symposium on Quality Electronic Design, pp. 56-61, San Jose, California, March 2001.
[22] Synopsys HSPICE.
http://www.synopsys.com/Tools/Verification/AMSVerification/CircuitSimulation/HSPICE/Pages/default.aspx
[23] Synopsys PrimeTime PX.
http://www.synopsys.com/Tools/Implementation/SignOff/Pages/PrimeTime.aspx
[24] D. Shin, H. Shim, Y. Joo, H.-S. Yun, J. Kim, and N. Chang, “Energy Monitoring Tool for Low-Power Embedded Programs,” IEEE Design and Test of Computers, Vol. 19, No. 4, pp. 7-17, July 2002.
[25] D. Brooks, V. Tiwari, and M. Martonosi, “Wattch: A Framework for Architectural-Level Power Analysis and Optimizations,” Proceedings of the 27th International Symposium on Computer Architecture, pp. 83-94, Vancouver, British Columbia, Canada, June 2000.
[26] W. Ye, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, “The Design and Use of SimplePower: A Cycle-Accurate Energy Estimation Tool,” Proceedings of the 37th Design Automation Conference, pp. 340-345, Los Angeles, California, June 2000.
[27] R. Ben Atitallah, S. Niar, and J.-L. Dekeyser, “MPSoC Power Estimation Framework at Transaction Level Modeling,” Proceedings of the 19th International Conference on Microelectronics, pp.245-248, Cairo, Egypt, December 2007.
[28] G. Contreras and M. Martonosi, “Power Prediction for Intel XScale Processors Using Performance Monitoring Unit Events,” Proceedings of the 10th International Symposium on Low Power Electronics and Design, pp. 221-226, San Diego, California, August 2005.
[29] G. Contreras, M. Martonosi, J. Peng, G.-Y. Lueh, and R. Ju, “The XTREM Power and Performance Simulator for the Intel XScale Core: Design and Experiences,” ACM Transactions on Embedded Computing Systems, Vol. 6, No. 1, February 2007.
[30] J. Gaisler, E. Catovic, M. Isom�驥i, K. Glembo, and S. Habinc, GRLIB IP Library User’s Manual Version 1.0.20, Aeroflex Gaisler, February 2009.
[31] GRMON User’s Manual Version 1.1.35, Aeroflex Gaisler, March 2009.
[32] ALTERA DE3 Development and Education Board User Manual, Terasic Technologies.
[33] Altera Quartus II.
http://www.altera.com/products/software/quartus-ii/subscription-edition
[34] D. Hellstr�卌, Manual: SnapGear Linux for LEON Version 1.38.0, March 2009.
[35] Synopsys Design Compiler.
http://www.synopsys.com/Tools/Implementation/RTLSynthesis/Pages/DesignCompilerGraphical.aspx
[36] Mentor Graphics ModelSim.
http://www.mentor.com/products/fv/modelsim
[37] S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta, “The SPLASH-2 Programs: Characterization and Methodological Considerations,” Proceedings of the 22nd International Symposium on Computer Architecture, pp. 24-36, Santa Margherita Ligure, Italy, June 1995.
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