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研究生:黃上賓
研究生(外文):Shang-Bin Huang
論文名稱:應用於無線近身網路之嵌入式晶體振盪器
論文名稱(外文):An Embedded Crystal Oscillator for Wireless Body Area Network Applications
指導教授:李鎮宜
指導教授(外文):Chen-Yi Lee
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:97
語文別:英文
論文頁數:61
中文關鍵詞:低功率功率閘嵌入式晶體振盪器頻率偵測器
外文關鍵詞:low powerpower gatingeCrystal oscillatorfrequency detector
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在本篇論文裡,我們介紹一個應用於無線近身網路的嵌入式晶體振盪器和基頻低功率設計流程,來降低整個系統的功率消耗和面積使用。

近年來,健康照護的系統應用於無線近身網路愈來愈受到人們的重視,尤其是針對人體生醫訊號的偵測。在這樣的應用中,可以從配戴在身上的無線感測器對人體訊號做長時間的偵測,並以無線的方式將資料傳送給整合在手機或個人數位助理的接收端。基於這樣的一個應用,極低的功率消耗跟高度整合的面積會是系統不可或缺的需求。我們使用了低功率的設計流程來降低整個基頻的功率消耗,儘管整個基頻的功率消耗已經非常低。但從整個系統來看,我們可以發現功率消耗主要由晶片外部的一些元件佔非常大的部份,像是石英晶體與其搭配使用的振盪器。不僅如此,這些晶片外部的元件同樣佔據了相當大的面積使用,對整個系統造成額外的負擔,於是嵌入式晶體振盪器[1]被提出來取代這些晶片外部所使用元件。嵌入式晶體振盪器是藉由互補金氧半導體製程的方式,將晶體振盪器整合進單一晶片中,如此一來可以大大地降低系統的製造成本、面積及功率消耗。在本篇論文我們對整個嵌入式晶體振盪器的行為做一個詳盡的闡述,並分析頻率校準的設計,最後建立了一個嵌入式晶體振盪器的原型來驗證這樣的行為。藉由使用嵌入式晶體振盪器以及基頻的低功率設計流程,整個系統將可以降低73%的功率消耗和53%的面積使用。
In this thesis we propose an Embedded Crystal (eCrystal) oscillator and baseband low power design flow for Wireless Body Area Network (WBAN) applications to assure the overall system power and area reduction.

In the recent years, people have attached great importance to healthcare monitoring system for WBAN applications. There are multiple wireless sensor nodes (WSNs) placed on the human body for long-time monitoring. The WSNs transmit data wirelessly to a central processing node (CPN) integrated into mobile phones or personal digital assistants (PDAs). Ultra-low power and tiny integrated area are the features required in such applications. A low power design flow comprising Multiple Supply Voltage (MSV) and power gating is used to reduce baseband power consumption. However, the overall system power is dominated by some off-chip components, e.g. quartz crystal and oscillator. Besides, these external components also occupy very large system area. Therefore, an eCrystal oscillator [1] has been proposed to replace these external components, and this can largely reduce manufacturing cost, system area, and power consumption. We elaborate and analyze the frequency error calibration of eCrystal oscillator and establish the prototype platform to verify the system behavior with eCrystal oscillator. By the use of eCrystal oscillator and baseband low power design flow, the system will have 73% power reduction and 53% area reduction.
Chapter 1 Introduction 1
1-1 Motivation 1
1-2 Organization 5
Chapter 2 Low Power Design Flow 6
2-1 Background 6
2-1-1 Multiple Supply Voltage 6
2-1-2 Power Gating 7
2-2 Low Power Design Flow 10
2-3 Implementations 11
2-3-1 Voltage/Power Domain Partitions 12
2-3-2 Power Gating Implementation 13
2-3-3 Power Gating and Isolation Timing Control 13
2-4 Measurement Results 16
Chapter 3 Analysis of Embedded Crystal Oscillator 20
3-1 System Overview 20
3-2 System Behavior 23
3-3 Frequency Detector 24
Chapter 4 Emulation of Embedded Crystal Oscillator 35
4-1 Building Block Design 36
4-1-1 Transmitter Node and Remote Reference 36
4-1-2 Clock Generator 36
4-1-3 Frequency Detector 37
4-1-4 A/D and D/A Interface 38
4-2 Case Studies 39
4-2-1 Frequency Shift Keying Applications 39
4-2-2 Wireless Body Area Network Applications 43
Chapter 5 Conclusions and Future Work 50
5-1 Conclusions 50
5-2 Future Work 50
References 52
Appendix 54
Supplementary of Power Gating Cell 54
[1] Chen-Yi Lee and Jui-Yuan Yu, “Crystal-less Communications Device and Self-Calibrated Embedded Virtual Crystal Clock Generation Method,” US/TW/JPA/Euro patent, Filed on Jul. 2008.
[2] Citizen [Online]. Available: http://www.citizencrystal.com
[3] Chen-Yi Lee, Jui-Yuan Yu, Chien-Ying Yu, and Juinn-Ting Chen, “Absolute Delay-Timing Generator,” US/TW/JPA/Euro patent, Filed on Jul. 2008.
[4] D. E. Lackey, P. S. Zuchowski, T. R. Bednar, D. W. Stout, S. W. Gould, and J. M. Cohn, “Managing Power and Performance for System-on-Chip Designs using Voltage Islands,” IEEE ACM International Conference on Computer Aided Design, ICCAD 2002, pp. 195-202, no. 10-14, Nov. 2002.
[5] S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu and J. Yamada, “1-V Power Supply High-Speed Digital Circuit Technology with Multi-threshold Voltage CMOS,” IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 847-854, Aug. 1995.
[6] J. T. Kao and A. P. Chandrakasan, “Dual-Threshold Techniques for Low-Power Digital Circuits,” IEEE J. Solid-State Circuits, pp. 1009-1018, Jul. 2000.
[7] K. Shi and D. Howard, “Sleep Transistor Design and Implementation - Simple Concepts Yet Challenges To Be Optimum,” International Symposium on VLSI Design Automation and Test, pp. 1-4, April 2006.
[8] Hsiao-Han Ma, Jui-Yuan Yu, Tsan-Wen Chen, Chien-Ying Yu, and Chen-Yi Lee, “An OFDMA Scheme Wireless Body Area Network with Frequency Pre-Calibration,” in Proc. 2008 IEEE VLSI-DAT, to be presented in Apr. 2008.
[9] Jui-Yuan Yu, Ching-Che Chung, Wan-Chun Liao, and Chen-Yi Lee, “A sub-mW Multi-Tone CDMA Baseband Transceiver Chipset for Wireless Body Area Network Applications,” ISSCC Dig. Tech. Papers, pp. 364-365, Feb. 2007.
[10] Yuan Chen, Yu-Wei Lin, and Chen-Yi Lee, “A Block Scaling FFT/IFFT Processor for WiMAX Applications,” IEEE Asian Solid-State Circuits Conference, pp. 203-206, Nov. 2006.
[11] A. L. Bramble, “Direct Digital Frequency Synthesis,” Proc. 35th annual Frequency Control Symposium, USERACOM, Ft. Monmouth, N.J., pp. 406-414, May 1981.
[12] Federal Communications Commission, “Amendment of Parts 2 and 95 of the Commission’s Rules to Create a Wireless Medical Telemetry Service ,” FCC Washington, D.C., Rep. FCC00-211, 2000.
[13] Juinn-Ting Chen, “A Tunable Clock Generator for Wireless Body Area Network Applications,” M.S. thesis, Dept. Electron. Eng., National Chiao Tung University, Hsinchu, Taiwan, 2008.
[14] Jinn-Shyan Wang, Hung-Yi Li, Ching-Wei Yeh, and Tien-Fu Chen, “Design Techniques for Single-Low-VDD CMOS Systems,” IEEE J. Solid-State Circuits, vol. 40, no. 5, May 2005.
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