臺灣博碩士論文加值系統

頻率合成器(Frequency Synthesizer)對於通訊晶片，無論是無線射頻傳輸介面或者高速的序列傳輸介面中，都扮演著非常重要的腳色，影響整個通訊晶片的性能甚大。隨著製程的進步，深次微米(Deep-submicrometer)的互補金氧半(CMOS)製程已廣泛地被應用於數位電路上，使得數位電路得以實現高度密集化、低成本與低功率消耗等需求。類比電路在低電壓的環境下，運作不易，不只增加設計上的難度，也使得類比電路無法隨著製程的演進，降低功率消耗。近年來，有些研究紛紛提出了數位控制振盪器(Digital Controlled Oscillator)的概念，藉由數位訊號來控制振盪器的振盪頻率，其中充電汞、迴路濾波器等的類比電路皆以數位電路取代，配合數位控制振盪器，使得整個迴路得以全數位化，較易操作在低電壓的工作環境下，使整體的功率能夠下降。
本作品實現一個具有低功率數位式自我校正頻率合成器，使用聯電90nm 1P9M互補金氧半製程實現，且適用於生物感測器(Bio-sensor)上的收發機(transceiver)，中央頻率為1.4GHz，預計功率消耗低於1mW；相位雜訊在距離載波頻率1MHz 時小於-100dBc/Hz。此外, 為兼顧低功率操作與性能穩定之雙重條件，本電路可依據 PVT 的變化自動調整硬體結構，以達到自我校準與操作性能之最佳化。

摘要 i
Abstract iii
致謝 v
Contents vi
List of Tables viii
List of Figures ix
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Overview of Thesis 4
Chapter 2 Architecture 5
2.1 Prior Art 5
2.2 Proposed Architecture of the Low Power ADPLL 9
Chapter 3 Analysis of the ADPLL 12
3.1 The Dynamics of the ADPLL 12
3.2 Linear Model of the ADPLL 13
3.2.1 Linear Model of the DCO 13
3.2.2 Linear Model of the Frequency Divider 14
3.2.3 Linear Model of the Bang-Bang PD 14
3.2.4 Linear Model of the Loop Filter 17
3.2.5 Linear Model of the Complete PLL Loop 19
3.3 Generated Phase Noise 19
3.3.1 Noise Model of the DCO 19
3.3.2 Noise Model of the BBPD 28
3.3.3 Output Phase Noise Power Spectral Density 29
Chapter 4 Design and Implementation 32
4.1 Phase Detector (PD) 32
4.2 Dynamic Loop Filter (DLF) 33
4.3 Calibration Digital Controlled Oscillator (CDCO) 35
4.3.1 Digital Controlled Oscillator (DCO) 35
4.3.2 DCO Calibration Circuit (DCC) 39
4.4 Frequency Divider 46
Chapter 5 Experimental Results 48
5.1 Layout and Chip Photo 48
5.2 Experimental Setup 51
5.3 Experimental Results 53
5.3.1 Open-Loop of the ADPLL 53
5.3.2 Closed-Loop of the ADPLL 58
5.4 Performance Summary 62
Chapter 6 Conclusion 63
Reference 64
簡歷 66

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