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研究生:陳世宏
研究生(外文):Chen, Shih-Hung
論文名稱:互補式金氧半積體電路靜電放電防護之設計最佳化與故障分析
論文名稱(外文):Design Optimization and Failure Analysis of On-Chip ESD Protection in CMOS Integrated Circuits
指導教授:柯明道柯明道引用關係
指導教授(外文):Ker, Ming-Dou
學位類別:博士
校院名稱:國立交通大學
系所名稱:電子工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:144
中文關鍵詞:互補式金氧半積體電路靜電放電全晶片靜電放電防護設計故障分析電源箝制靜電放電防護電路主動式跨電源組靜電放電防護電路
外文關鍵詞:CMOS Integrated CircuitsElectrostatic DischargeESDOn-Chip ESD Protection DesignFailure AnalysisPower-Rail ESD Clamp CircuitActive Cross-Power-Domain ESD Protection Circuit
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隨著奈米尺度互補式金氧半製程時代的來臨與系統單晶片應用的持續發展,靜電放電(Electrostatic Discharge, ESD)防護已成為積體電路產品可靠度中相當艱鉅的挑戰。為避免積體電路遭受靜電放電的威脅與破壞,所有積體電路與外界接觸的輸入輸出銲墊(Pad)或是電源銲墊,皆須搭配靜電放電防護設計。然而,輸入輸出銲墊上的靜電放電防護電路會在訊號路徑上產生寄生效應。若訊號路徑上的寄生效應過大,將導致電路性能的嚴重衰減。尤其於類比輸入輸出界面電路與跨電源組之內部傳輸界面電路應用中,靜電放電防護電路在訊號路徑上引起的寄生效應必須達到最小化的設計。寄生效應嚴格限制的情況下,電源箝制靜電放電防護電路(Power-Rail ESD Clamp Circuit)是達成積體電路產品全晶片靜電放電防護極為有效的設計。它不僅可以提升電源線至接地線的靜電放電防護能力,亦能顯著強化輸入輸出銲墊至電源線(VDD)與接地線(VSS)或是接點對接點(Pin-to-Pin)的靜電放電防護能力。搭配電源箝制靜電放電防護電路與類比輸入輸出銲墊的靜電放電防護電路,將可共構出適用於類比輸入輸出界面電路的低寄生效應靜電放電防護電路。此外,跨電源組內部傳輸界面電路的靜電放電防護問題,亦可利用電源箝制靜電放電防護電路與主動式跨電源組靜電放電防護電路(Active Cross-Power- Domain ESD Protection Circuit)成功獲得解決。具備有效且可靠的靜電放電防護設計,能夠提供奈米尺度積體電路產品足夠的耐用年限,並能讓產品使用者更加安心。
為獲得良好的靜電放電防護能力,擁有閘極驅動機制的N型金氧半電晶體電源箝制靜電放電防護電路,已經廣泛使用於奈米尺度互補式金氧半製程技術的積體電路產品。這些電源箝制靜電放電防護電路具有一特定電路架構,即是以多級反相器(Multi-Stage Inverters)實現控制電路,驅動主靜電放電箝制N型金氧半電晶體(Main ESD Clamp NMOS Transistor)。本論文的第二章分析兩種控制電路架構,分別為三級反相器與一級反相器,對於靜電放電防護與應用所造成的影響,藉以驗證適用於電源箝制靜電放電防護電路的最佳化設計。研究中發現不良的電路設計架構,會導致N型金氧半電晶體的電源箝制靜電放電防護電路,在電性高速暫態(Electrical Fast Transient, EFT)測試與高速電源啟動(Fast Power-On)測試下,發生異常的閂鎖導通現象(Latch-On Event)。本章後段利用高敏度微光顯微鏡(Emission Microscope, EMMI),清楚解釋電源箝制靜電放電防護電路的異常閂鎖導通故障機制。
除了控制電路以外,N型金氧半電晶體電源箝制靜電放電防護電路的靜電放電暫態偵測電路(ESD-Transient Detection Circuit)亦是決定電源箝制靜電放電防護電路性能與應用的關鍵因素。本論文第三章提出了一個嶄新的靜電放電暫態偵測電路,其特點為極小的靜電放電暫態偵測電容設計下,成功延長主靜電放電箝制N型金氧半電晶體導通時間,進而提升電源箝制靜電放電防護電路的導通效率與靜電放電耐受度。此外,這個靜電放電暫態偵測電路擁有優異抵抗誤觸發(Mis-Trigger)與閂鎖導通的能力,可以安全使用於高速電源啟動的特殊電路系統。
在電源箝制靜電放電防護電路的設計中,主靜電放電箝制元件(Main ESD Clamp Device)將是直接影響靜電放電防護能力的最主要因素。一直以來,矽控整流器元件(Silicon Controlled Rectifier, SCR)即是以極高的單位面積靜電放電耐受度而備受矚目。然而過高的觸發電壓與較差的導通速度,使得矽控整流器元件在先進製程的靜電放電防護應用上受到很大的限制。本論文的第四章提出具有低觸發電壓與高導通效率的常開型效能矽控整流器設計(Initial-On SCR Design)。未使用特殊的常開型元件與未進行製程調整的情況下,以矽控整流器元件搭配內嵌P型金氧半電晶體做為觸發控制電路完成常開型效能矽控整流器設計,適用於一般的互補式金氧半製程技術,大大增加矽控整流器元件於深次微米與奈米尺度積體電路的靜電放電防護應用。此外,這個常開型效能的矽控整流器於2.5伏特的操作電壓下擁有足夠高的導通電壓(Holding Voltage, Vh),可避免電性閂鎖(Latchup)的問題。經由實驗晶片量測結果,以P型金氧半電晶體觸發的常開型效能矽控整流器,已成功驗證於0.25微米互補式金氧半製程技術。
本論文第五章針對前一章所提出的金氧半電晶體觸發矽控整流器(MOS-Triggered SCR)元件進行設計最佳化的分析與研究。金氧半電晶體觸發矽控整流器元件的觸發機制與靜電放電電流分佈會受到內嵌金氧半電晶體的通道長度的改變而有所不同,通道長度將對於矽控整流器元件的觸發電壓(Trigger Voltage, Vt1)、導通電壓、導通電阻(On Resistance, Ron)、二次崩潰電流(Second Breakdown Current, It2)與靜電放電耐受度有相當大的影響。為使金氧半電晶體觸發矽控整流器於深次微米與奈米尺度的積體電路之靜電放電防護應用中達到最佳效能,內嵌金氧半電晶體的通道長度與電路佈局設計最佳化已透過各項參數的分析比較呈現於第五章。
於類比輸入輸出界面電路的應用中,本論文第六章以兩種類比輸入輸出銲墊的靜電放電防護電路,搭配不同的電源箝制靜電放電防護電路進行設計最佳化研究。本章使用0.18微米1.8伏特與3.3伏特互補式金氧半製程技術,分別設計了四種可應用於類比輸入輸出界面電路的靜電放電防護電路。其中,分析三種電源箝制靜電放電箝制元件分別為閘極驅動N型金氧半電晶體(Gate-Driven NMOS)、基體觸發的場氧化層元件(Substrate-Triggered Field-Oxide Device, STFOD)與基體觸發N型金氧半電晶體(Substrate-Triggered NMOS, STNMOS),在類比輸入輸出界面電路的電源箝制靜電放電防護電路中的防護效能,藉以找出適當的電源箝制靜電放電箝制元件。經由實驗晶片量測結果,在0.18微米的互補式金氧半製程技術中,適用於類比輸入輸出界面電路的靜電放電防護設計,是以雙二極體(Double Diode)作為類比輸入輸出銲墊上的靜電放電防護電路,這兩個二極體分別放置於類比輸入輸出銲墊至電源線與接地線間,搭配閘極驅動N型金氧半電晶體電源箝制靜電放電防護電路。經由掃瞄式電子顯微鏡的觀察,四種類比輸入輸出電放電防護設計的故障機制,獲得更完整的分析與討論。施加負靜電放電電壓於類比輸入輸出銲墊且電源線接地的測試條件(Negative-to-VDD Mode, ND-Mode)下,以雙二極體與基體觸發場氧化層元件所建構的類比輸入輸出靜電放電防護設計,產生了異常的故障點。這個故障機制是由於寄生於靜電放電防護二極體與N型防護環(Guard Ring)間的npn雙極性接面電晶體(Bipolar Junction Transistor, BJT)意外觸發導致大量靜電放電電流,經這個寄生npn雙極性接面電晶體釋放造成防護環的燒熔破壞。本章的最後針對此故障機制提出相對應的解決方案。
由於積體電路設計的複雜化,越來越多的電路功能整合入同一個單晶片上,而這些電路區塊因為操作電壓的不同與電源雜訊耦合的考量,各自擁有獨立的電源組,然而這樣的獨立電源組架構相當不利於跨電源組靜電放電防護,使得跨電源組靜電放電防護設計成為極需被解決的問題。本論文第七章首先探討了一件積體電路產品的跨電源組界面電路故障案例。於此案例中,產品的人體放電模式靜電放電耐受度可以達到2000伏特,但其機械放電模式靜電放電耐受度則無法達到150伏特。施加負靜電放電電壓於輸入輸出銲墊且電源線接地的機械放電模式的測試條件下,靜電放電電流經由跨電源組界面電路釋放,造成界面電路的閘極氧化層、接面與接觸(Contact)的嚴重燒熔破壞。藉由故障分析技術,清楚分析跨電源組靜電放電電流釋放路徑與故障機制。本章的第二部分,針對目前已發表的跨電源組界面電路靜電放電防護設計進行分析,藉以更進一步了解跨電源組間靜電放電防護設計策略。在本章的最後一部份,提出了適用於跨電源組界面電路的主動式跨電源組靜電放電防護設計,並且於130奈米互補式金氧半製程技術中獲得成功的驗證。於跨電源組人體放電模式與機械放電模式靜電放電測試中,其靜電放電耐受度分別達到4000伏特與400伏特。
第八章總結本論文的研究成果,並提出數個接續本論文研究方向的研究題目。本論文所提出的各項新型設計,均搭配實驗晶片量測結果以驗證設計之理論,且有相對應的國際期刊與國際研討會論文發表。本論文中數個創新設計已提出專利申請。
With the era of the advanced nanoscale CMOS technology and the development of system-on-chip (SoC) application, electrostatic discharge (ESD) protection has become a tough challenge on the product reliability of CMOS integrated circuits. ESD protection must be taken into consideration during the design phase of all IC products. In order to prevent the ESD failures and damages in IC products, all pads which connect the IC and the external world need to be provided with ESD protection circuits, including the input/output (I/O) pads, VDD pads, and VSS pads. However, the ESD protection devices at the I/O pads inevitably cause parasitic effects on the signal path. If the parasitic effects on the signal path are too large, the circuit performance will be seriously degraded. In other words, the parasitic effects which are induced by ESD protection on the signal paths need to be minimized, especially in analog I/O interface circuits and internal transmission interface circuit between separated power domains. The power-rail ESD clamp circuit is an efficient design to achieve whole-chip ESD protection in IC products. It not only can enhance ESD robustness of VDD-to-VSS ESD stress, but also can significantly improve ESD robustness of the ESD stresses between input/output and VDD/VSS or pin-to-pin combinations. A turn-on efficient power-rail ESD clamp circuit between VDD and VSS is co-constructed into the analog ESD protection circuit to improve the overall ESD level of the analog I/O interface circuits. Moreover, the ESD issues of interface circuits between separated power domains also can be solved by turn-on efficient power-rail ESD clamp circuit cooperated with active cross-power-domain ESD protection designs. With efficient on-chip ESD protection designs, the integrated circuits with nanoscale CMOS technology can be safely used and provide moderate life time.
NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the desired ESD protection capability. All of them are usually based on a similar circuit scheme with multiple-stage inverters to drive the main ESD clamp NMOS transistor with large device dimension. In Chapter 2, the designs with 3-stage-inverter and 1-stage-inverter controlling circuits have been studied to verify the optimal circuit schemes in the NMOS-based power-rail ESD clamp circuits. Besides, the circuit performances among the main ESD clamp NMOS transistors drawn in different layout styles cooperated with the controlling circuit of 3-stage inverters or 1-stage inverter are compared. Among the NMOS-based power-rail ESD clamp circuits, an abnormal latch-on event has been observed under the EFT test and fast power-on condition. The root cause of this latch-on failure mechanism has been clearly explained by the emission microscope with InGaAs FPA detector.
Besides controlling circuit in NMOS-based power-rail ESD clamp circuit, a power-rail ESD clamp circuit with a new proposed ESD-transient detection circuit of ultra small capacitor has been presented and verified to possess a long turn-on duration and high turn-on efficiency in chapter 3. In addition, the power-rail ESD clamp circuit with the proposed ESD-transient detection circuit also showed an excellent immunity against the mis-trigger and the latch-on event under the fast power-on condition.
In chapter 4, a novel SCR design with “initial-on” function is proposed to achieve the lowest trigger voltage and the highest turn-on efficiency of SCR device for effective on-chip ESD protection. Without using the special native device (NMOS with almost zero or even negative threshold voltage) or any process modification, this initial-on SCR design is implemented by PMOS-triggered SCR device, which can be realized in general CMOS processes to enhance the applications of SCR devices for deep-submicron or nanoscale CMOS technology. This initial-on SCR design has a high enough holding voltage to avoid latchup issues in a VDD operation voltage of 2.5 V. The new proposed initial-on ESD protection design with PMOS-triggered SCR device has been successfully verified in a fully-silicided 0.25-μm CMOS process.
In chapter 5, the channel length of the embedded MOS transistor in the MOS-triggered SCR device has been demonstrated to dominate the trigger mechanism and current distribution to govern the trigger voltage, holding voltage, on resistance, second breakdown current, and ESD robustness of the MOS-triggered SCR device. MOS-triggered SCR devices have been reported to achieve efficient on-chip ESD protection in deep-submicron or nanoscale CMOS technology. The embedded MOS transistor in the MOS-triggered SCR device should be optimized to achieve the most efficient ESD protection in advanced CMOS technology. In addition, the layout style of the embedded MOS transistor can be adjusted to improve the MOS-triggered SCR device for ESD protection.
In chapter 6, different ESD protection schemes have been investigated to find the optimal ESD protection design for analog I/O buffer in a 0.18-µm 1.8-V and 3.3-V CMOS technology. Three power-rail ESD clamp devices, which are gate-driven NMOS, substrate-triggered field-oxide device (STFOD), and substrate-triggered NMOS (STNMOS) with dummy gate, are used for power-rail ESD clamp circuits to compare the protection efficiency in analog I/O applications. From the experimental results, the pure-diode ESD protection devices and the power-rail ESD clamp circuit with gate-driven NMOS are the suitable design for analog I/O buffer in the 0.18-�慆 CMOS process. Each ESD failure mechanism was inspected by SEM photograph in all analog I/O pins. An unexpected failure mechanism was found in the analog I/O pins with pure-diode ESD protection design under ND-mode ESD stress. The parasitic npn bipolar transistor between ESD clamp device and guard ring structure was triggered to discharge the ESD current and cause damage under ND-mode ESD stress.
Chapter 7 presents several complex ESD failure mechanisms in the interface circuits of an IC product with multiple separated power domains. In this case, the MM ESD robustness can not achieve 150 V in this IC product with separated power domains, although it can pass the 2-kV HBM ESD test. The ND-mode MM ESD currents were discharged by circuitous current paths through interface circuits to cause the gate oxide damage, junction filament, and contact destroy of the internal transistors. The detailed discharging paths of ND-mode ESD failures were analyzed in this paper. In addition, some ESD protection designs have been illustrated and reviewed to further comprehend the protection strategies for cross-power-domain ESD events in chapter 7. Moreover, one new active ESD protection design for the interface circuits between separated power domains has been proposed and successfully verified in a 0.13-�慆 CMOS technology. The HBM and MM ESD robustness of the separated-power-domain interface circuits with the proposed active ESD protection design can achieve over 4 kV and 400 V, respectively.
Chapter 8 concludes the achievement in this dissertation, and suggests several future works in this research field. In this dissertation, several novel designs have been proposed in the aforementioned research topics. Measured results of fabricated test chips have demonstrated the performance improvement. The achievement of this dissertation has been published in several international journal and conference papers. Several innovative designs have been applied for patents.
1. Introduction 1
1.1. Background of ESD Protection Design for
Integrated Circuits in Advanced CMOS
Technologies 1
1.1.1. Issues of ESD-Transient Detection Circuit and
Controlling Circuit 6
1.1.2. Issue of SCR Device as Main ESD Clamp Device 7
1.2. ESD Issues in Analog I/O and Multiple Separated
Power Domains Interface Circuits 9
1.3. Organization of This Dissertation 13

2. Evaluation on NMOS-Based Power-Rail ESD Clamp
Circuits with Gate-Driven Mechanism 17
2.1. Power-Rail ESD Clamp Circuits with Different
Controlling Circuits and Layout Styles for Main
ESD Clamp NMOS 17
2.1.1. Influence of the RC-Time Constants 17
2.1.2. Controlling Circuits and Layout Styles 18
2.2. ESD Protection Designs by Circuit Solutions 20
2.2.1. DC Leakage Current 20
2.2.2. Turn-On Verification under ESD-Like Stress
Condition 22
2.2.3. TLP I-V Characteristics and HBM ESD Robustness 24
2.2.4. Power-On Condition and Normal Circuit Operation
Condition 28
2.3. Experimental Results in System-Level Test 30
2.3.1. Electrical Fast Transient (EFT) Test 30
2.3.2. Latch-On Mechanism 34
2.4. Summary 37

3. Area-Efficient ESD-Transient Detection Circuit
with Ultra Small Capacitance for On-Chip Power-
Rail ESD Protection in CMOS ICs 38
3.1. Background 38
3.2. Realization of Power-Rail ESD Clamp Circuit 40
3.2.1. New Proposed ESD-transient Detection Circuit 40
3.2.2. Operation Principles 41
3.3. Experimental Results 43
3.3.1. Turn-On Verification under ESD-Like Stress
Condition 43
3.3.2. TLP I-V Characteristics and ESD Robustness 44
3.3.3. Fast Power-On Condition and Discussion 46
3.4. Summary 48

4. Implementation of Initial-On ESD Protection
Concept with PMOS- Triggered SCR Devices in Deep-
Submicron CMOS Technology 49
4.1. Background 49
4.2. Realization of the Initial-On SCR Design 51
4.2.1. Implementation of the Initial-On ESD Protection
Circuit 51
4.2.2. Operation Principles 52
4.2.3. Layout Structure for Initial-On SCR Device 53
4.3. Experimental Results 54
4.3.1. DC Characteristics for the Initial-On SCR
Devices 54
4.3.2. Turn-on Verification 57
4.3.3. TLP Characteristics 60
4.3.4. ESD Robustness 62
4.4. Applications for On-Chip ESD Protection 63
4.4.1. Whole-Chip ESD Protection Scheme 63
4.4.2. ESD Protection for IC with Multi-Power Domains 65
4.4.3. Discussion 66
4.5. Summary 69

5. Optimization on MOS-Triggered SCR Structures for
On-Chip ESD Protection 70
5.1. SCR Devices with Embedded MOS Transistors 70
5.2. Experimental Results 73
5.2.1. Device Characteristics of the MOS-Triggered SCR
Devices 73
5.2.2. Turn-on Verifications of the MOS-Triggered SCR
Devices 75
5.2.3. TLP I-V Characteristics and ESD Robustness 77
5.3. Failure Analysis and Discussion 80
5.3.1. Failure Analysis 80
5.3.2. Discussion 82
5.4. Summary 84

6. ESD Failure Mechanisms of Analog I/O Cells in a
0.18-um CMOS Technology 85
6.1. ESD Protection Schemes for Analog I/O Interface
Circuits 85
6.1.1 ESD Protection Circuit 85
6.1.2 Turn-On Efficiency of Power-Rail ESD Clamp
Circuit 89
6.2. Experimental Results and Dscussion 91
6.2.1 HBM ESD Robustness 92
6.2.2 Failure Analysis 93
6.2.3 Unexpected Failure Spot in ND-mode ESD Stress 100
6.3. Summary 102

7. Active ESD Protection Design for Interface
Circuits between Separated Power Domains against
Cross-Power-Domain ESD Stresses 103
7.1. Failure Study under Cross-Power-Domain ESD
Stresses 103
7.1.1 ESD Protection Cell Designs for the Commercial IC
Product with Separated Power Pins 103
7.1.2 Internal ESD Damages on the Interface Circuits
between Separated Power Domains 104
7.1.3 Failure Mechanism under Cross-Power-Domain ESD
Stresses 106
7.1.4 Proposed Solutions to Rescue such ESD Failures 109
7.2. Active ESD Protection Designs for Interface
Circuits between Separated Power Domains 110
7.2.1. ESD Threats and Damages of Interface Circuits
between Separated Power Domains 110
7.2.2. Review on ESD Protection Designs for Interface
Circuits between Separated Power Domains 112
7.3. New Cross-Power-Domain ESD Protection Design 115
7.3.1. Implementation of the New Proposed Design for
Cross-Power-Domain ESD Protection 115
7.3.2. Experimental Results 117
7.3.3. Failure Analysis and Discussion 121
7.4. Summary 125

8. Conclusions and Future Works 126
8.1 Main Results of This Dissertation 126
8.2 Future Works 129

References 131
Vita 139
Publication List 141
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[76] JEDEC Standard JESD22-C101-A, Field-Induced Charged-Device Model Test Method for Electrostatic Discharge Withstand Thresholds of Microelectronic Components, 2000.
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