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研究生:陳名瑜
研究生(外文):Chen, Ming-Yu
論文名稱:應用於超高速傳輸多天線系統(MIMO-OFDM)頻域上之高時脈誤差容忍時間同步器
論文名稱(外文):Frequency-Domain Timing Synchronizer with Wide Clock Offset Tolerance in Very-High-Throughput MIMO-OFDM Systems
指導教授:張立平張立平引用關係
指導教授(外文):Chang, Li-Pin
學位類別:碩士
校院名稱:國立交通大學
系所名稱:多媒體工程研究所
學門:電算機學門
學類:軟體發展學類
論文種類:學術論文
畢業學年度:97
語文別:英文
論文頁數:29
中文關鍵詞:時間同步取樣偏移正交分頻
外文關鍵詞:Timing SynchronizationSampling Clock OffsetOFDM
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隨著無線通訊技術的快速發展,超高速傳輸系統已成為新一代無線通訊系統的發展核心,然而高速傳輸需要更快的取樣頻率,這將使得「大量取樣頻率偏移」此問題發生的機率增加,這將造成訊號嚴重的衰減。因此,本論文致力於研究在2048-FFT下超高速多天線正交分頻多工系統中(MIMO OFDM),頻率域上的時間同步器,並以調節取樣相位的方式補償取樣頻脈誤差,達到同步取樣的目的。
本論文所提出的演算法,主要應用在 IEEE 所制定的無線區域網路標準 IEEE 802.11n,藉由利用封包前端格式固定的preambles,針對其彼此間的相關性對取樣頻率誤差作估計以及補償。此演算法中,總共使用六個preambles。在高斯雜訊及多路徑衰減的情形下,以封包錯誤率(PER)小於8%為標準,效能可以達到容忍-30000~40000-ppm的時脈偏移影響。
Due to the explosive growth demand for wireless communication, the next-generation wireless communication systems are expected to provide high-speed and high-throughput. However, high-speed transmission needs high sampling rate, which would cause wide sam-pling clock offset. Based on phase adjustment, this work investigates a frequency-domain timing synchronizer to perform coherent sampling for 2048-FFT Multiple-Input Mul-tiple-Output (MIMO) Orthogonal Frequency Division Multiplexing (OFDM) timing recov-ery.
In the proposed algorithm, we use a multiphase all-digital clock management (ADCM) which can generate more than 32 phases over GHz without phase-locked or delay-locked loops to adjust sampling phases and utilize the correlation between short preambles to es-timation the sampling phase error. It can perform the sampling clock synchronization effi-ciently and quickly. Performance evaluation indicates that the proposed timing synchronizer can tolerate -30000 ~ 40000ppm sampling clock offsets with 0.2db SNR losses at 8% PER in frequency-selective fading. Hence, this scheme involves a little overhead to ensure fast recovery and wide offset tolerance for OFDM packet transmissions.
CHAPTER1 INTRODUCTION …………………………………….…………………..1

CHAPTER2 SYSTEM ASSUMPTIONS ……………………..………………………4
2.1 IEEE 802.11n Physical Layer Specification …………………………………...4
2.1.1 Transmitter ……….……………………………………………………...4
2.1.2 Receiver …………………………………………………………………..5
2.1.3 Basic MIMO PPDU Format …………………………………………….5
2.2 Channel model ………………………….…………………………………….....6
2.2.1 Additive White Gaussian Noise …….…………………………………...6
2.2.2 Multipath ...……….……………………………………………………....7
2.2.3 Sampling Clock Offset ...………………………………………………....8
2.3 Problem statement …..………………….…………………………………….....9

CHAPTER3 FD- TIMING SYNCHRONIZER ….........................................................10
3.1 Sampling clock offset estimation ……………………………………………...10
3.2 Sampling phase acquisition …………………………………………………....15
3.3 Combine sampling phase acquisition and SCO estimation ….........................19
3.4 Compensation ………………………………………………………………......20

CHAPTER4 SIMULATION ………….………………………………………………..22
4.1 Simulation platform …………….……………………………………………...22
4.2 Simulation result ……………………………………………………………….22

CHAPTER5 HARDWARE IMPLEMENTATION …………………………………..25

CHAPTER6 CONCLUSIONS AND FUTURE WORKS …………………………….27

REFERENCES ……………………………………………………...…………………...28
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