臺灣博碩士論文加值系統

本篇論文針對穩態視覺誘發電位之腦電訊號處理設計數位訊號處理電路，實現具即時性的大腦人機介面系統。旨在改善目前相關研究必須建構於使用個人電腦搭配線上訊號處理軟體以及資料擷取卡等的高成本實現方式。本研究以FPGA為基礎的實現方式，設計相當電路實現SSVEP之硬體即時信號處理電路，用以建立低成本與方便使用的BCI系統。另外，為有效誘發SSVEP之腦電訊號，本篇論文設計LED閃爍燈電路以視覺刺激方式誘發，為辨別多組LED閃爍燈以FPGA實現單頻多相位編碼技術產生多組訊號驅動之。最後經由實驗結果證明本系統確能有效誘發出使用者之 SSVEP，達成即時SSVEP信號處理，並且能有高準確辨識率。

This thesis mainly at the design of an electroencephalogram (EEG) digital signal processing circuit of steady state visual evoked potential (SSVEP) to implement a real time brain computer interface (BCI) system. In order to improve the relevant BCI researches take quite a few of cost on implement through personal computer, online signal processing software and data acquisition card. The FPGA-based implementation method is proposed to establish a low cost and easy to use BCI system through design the hardware real time signal processing circuit of SSVEP. Moreover, in order that the EEG signal of SSVEP is evoked availably, design a light emitting diode (LED) flicker light circuit and the visual stimulated method is proposed in this paper. And in order to indentify lots of LED flicker light is driven through the single frequency and multi phase encoding technique from FPGA. Finally, the system is verification that the SSVEP of user can be evoked availably, real time signal processed and higher accuracy rate form the experiment result.

目錄
中文摘要 I
英文摘要 II
致謝 III
目錄 IV
圖目錄 VI
表目錄 VIII
第一章 緒論 01
1.1 研究動機 01
1.2 研究背景 02
1.3 研究目的與方法 03
1.4 論文大綱 04
第二章 以穩態視覺誘發電位為基礎之大腦人機介面系統 05
第三章 大腦人機介面之數位訊號處理系統 10
3.1 系統相位編碼與辨識方法 10
3.1.1 單頻四相位編碼技術 11
3.1.2 視覺誘發腦電波相位辨識方法 12
3.2 使用者最佳化模式與應用模式 13
3.3 生理回饋系統 25
第四章 數位訊號處理系統之硬體實現 27
4.1 系統架構與FPGA核心簡介 27
4.2 訊號雜訊去除電路 30
4.2.1 數位濾波器 30
4.2.2 平均技術 31
4.3 周邊應用電路 33
4.3.1 類比/數位與數位/類比轉換電路 33
4.3.2 語音(音訊)應用電路 35
4.3.3 射頻模組 TG-11 應用電路 38
第五章 實驗結果與系統硬體模擬驗證 39
5.1系統規格與時間分析 39
5.2數位硬體驗證 44
5.2.1 數位濾波器與平均技術之硬體驗證 45
5.2.2 SPI控制器與其他電路硬體驗證 49
5.2.3 系統硬體邏輯單元的消耗程度 51
5.3大腦人機介面系統硬體驗證與實驗數據 52
5.4 實驗結果討論 55
第六章 結論與未來展望 59
參考文獻 60
作者簡歷 63

[1]J. Dunchen and T.Y. Hohrel, "A model of EMG generation", IEEE Trans. Biomed. Eng., Vol. 47, No. 2, Feb., 2000.
[2]L.A. Farwell, E. Donchin, "Talking off the top of your head:A mental prosthesis utilizing event-related brain potentials", Electroenceph Clin. Neurophysiol., Vol. 70, Dec., 1988.
[3]M. Cheng, X. Gao, S. Gao, and D. Xu, “Design and Implementation of a Brain-Computer Interface With High Transfer Rates,” IEEE Trans. Biomed. Eng., Vol. 49, No. 10, Oct., 2002.
[4]X. Gao, D. Xu, M. Cheng, and S. Gao, “A BCI-Based Environmental Controller for the Motion-Disabled,” IEEE Trans. Neural Syst. Rehab. Eng., Vol. 11, No. 2, Jun., 2003.
[5]L. J. Trejo, R. Rosipal, and B. Matthews, “Brain-Computer Interfaces for 1-D and 2-D Cursor Control: Designs Using Volitional Control of the EEG Spectrum or Steady-State Visual Evoked Potentials,” IEEE Trans. Neural Syst. Rehab. Eng., Vol. 14, No. 2, Jun., 2006.
[6]P.L. Lee, C.H. Wu, J.C. Hsieh, and Y.T. Wu, “visual evoked potemtial actuated brain computer interface: a brain-actuated cursor system”, Electronics Letters, vol. 41, No. 15, July, 2005
[7]謝竣傑，「多頻相位編碼之閃光視覺誘發電位驅動大腦人機介面」，國立中央大學電機工程學系，碩士論文，民國九十六年七月。
[8]J.R. Wolpaw, N. Birbaumer, W.J. Heetderks, "Brain computer interface technology：review of the first international meeting", IEEE Trans., Rehab Eng., Vol. 8, June., 2000.
[9]T.M. Vaughan, "Guest editorial brain-computer interface technology: a review of the second international meeting", IEEE Trans., Rehab Eng., Vol. 11, No. 2, June., 2003
[10]G. Schalk, D. J. McFarland, T. Hinterberger, N. Birbaumer, and J. R. Wolpaw, “BCI2000: A General-Purpose Brain-Computer Interface (BCI) System,” IEEE Trans. Biomed. Eng., Vol. 51, No. 6, Jun., 2004.
[11]E. C. Lalor, S. P. Kelly, C. Finucane, R. Burke, R. Smith, R. B. Reilly, and G. McDarby, “Steady-State VEP-Based Brain-Computer Interface Control in an Immersive 3D Gaming Environment,” EURASIP J. Appl. Signal Process., 19, pp. 3156-3164, 2005.
[12]Y. Wang, R. Wang, X. Gao, B. Hong, and S. Gao, “A Practical VEP-Based Brain-Computer Interface,” IEEE Trans. Neural Syst. Rehab. Eng., Vol. 14, No. 2, Jun., 2006.
[13]E.E. Sutter, “The brain response interface: communication through visually-induced electrical brain response”, J. Microcomputer Appl., Vol. 15, Jan., 1992
[14]程湘君，「信號與系統」，儒林圖書有限公司，民國八十五年五月。
[15]Bhaskar D. Rao, “Floating Point Arithmetic and Digital Filters”, IEEE Trans. Signal Proc., Vol. 40, No. 1, Jun., 1992.
[16]A. Golmohammadi, M.T. Manzuri and S. Ayat, “A new pipeline implementation of an adaptive IIR filter for noise reduction application”, in Proc. IEEE Conf. ISCIT., Vol. 1, Oct., 2004
[17]R.Jr Landry, V. Calmettes and E. Robin, “High speed IIR filter for XILINX FPGA”, in Proc. IEEE Conf. MWSCAS., Aug., 1998
[18]Microchip Technology Inc., MCP3201 Datasheet, Jan. 2008
[19]Microchip Technology Inc., MCP4921 Datasheet, Dec. 2006
[20]Microchip Technology Inc., 25LC1024 Datasheet, Jan. 2008
[21]Cyclone II Device Handbook, Altera, Inc., San Jose, CA, 2007.
[22]Quartus II Version 5.0 Handbook, Altera, Inc., San Jose, CA, 2005.