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研究生:陳欣伶
研究生(外文):Hsin-Ling Chen
論文名稱:兼具睡眠電流易測性與降低尖峰電流之低面積可調適資料保存邏輯設計
論文名稱(外文):Area-Efficient Adaptive Data-Retention Logics Simultaneously for Spike Reduction and IDDS Testability
指導教授:黃宗柱
指導教授(外文):Tsung-Chu Huang
學位類別:碩士
校院名稱:國立彰化師範大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:97
語文別:中文
論文頁數:103
中文關鍵詞:漏電流功耗靜態電流測試法資料保存
外文關鍵詞:leakage power dissipationIDDQData retention
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奈米製程系統晶片設計為當前電子設計自動化的重點,而奈米製程的漏電流、不確定性與系統晶片的測試、功耗與效能,均成為系統晶片設計自動化的關鍵問題。
由於標準元件設計是系統晶片設計自動化的基本流程,本研究利用多門檻電壓CMOS製程發展出一種同時達到低功、高速與電流可測性的邏輯標準元件之結構,使電路能逼近低門檻電壓CMOS的速率外,甦醒時間的縮短與尖峰功耗的降低,更能使電路系統在一個週期內,不預警以電源閘控休眠或甦醒繼續運算。
此外,我們亦發展出一套創新的電源閘控睡眠電流測試法,利用睡眠模式下具有資料保留之功能,使用本元件庫設計的電路系統可以在睡眠狀態下進行電流測試,改善約100倍左右的電流解析度,將使得電流測試再度成為一種極有效的缺陷測試法。
本研究並發展出一套完整的自動化流程與元件特徵萃取工具,以便將來在90奈米至65奈米製程下,能縮短設計的實現時間。現階段以台積電0.13μm製程技術完成一套基本CMOS邏輯元件庫,由實驗結果分析,雖然提出之ADR-CMOS結構的每個元件之額外面積需要53%,但總晶片僅需花費額外7.3%的面積。就電流平均而言,電流解析度可以大於40dB的改善,即100倍的電流改善率。
SoC design in nanotechnology has become the most significant topic in electronic de-sign automation. However, uncertainty in nanotechnology and testing, power dissipation, and performance for SoC design are simultaneously the critical issues.
Since cell-based design has become the basic and major design flow in SoC design automation, in this paper, a cell library in an MTCMOS technology is developed simultane-ously for low power, high speed and high current-testability. Not only the proposed structure can achieve a high speed approaching to low-threshold CMOS, but spike reduction and wakeup acceleration can also facilitate the circuit to fall asleep or to wake up within a clock cycle in the instant power management system.
Additionally, a novel power-gating sleep current testing scheme is developed so that the current resolution can be improved up to 100 times taking the advantages of data retention in proposed structure. This will make the current test renascent as an effective and efficient test method.
Automation is also planned to reduce implementation time under nanotechnology mi-gration by developing a design flow including tools and cell characterization. In present stage, TSMC 0.13 μm technology is employed to implement a set of adaptive data-retention CMOS cell library. From an example in a 130μm technology, although about 53% of extra area is needed for each logic cells, only 7.3% of area overhead is spent for the total chip. On average, the current resolution can be improved by more than 40 dB, i.e. 100 times of current resolu-tion improvement.
中文摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vii
表目錄 x
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 5
1.3 研究目的 7
1.4 本論文架構編排 8
第二章 漏電流功耗管理與測試考量之相關介紹 9
2.1 測試方式考量 9
2.1.1 測試程序的開發 (Test Program Development) 10
2.1.2 自動測試設備的測試類型 (ATE Test Types) 11
2.1.3 IDDQ測試概念 13
2.2 漏電流結構分析 16
2.3 功率消耗來源形式與評估 19
2.4 提出相關漏電流之研究與改善 21
2.4.1 使用電流檢測器之相關技術 21
2.4.2 調整設計MOS電晶體偏壓之相關技術 22
2.4.3 電源閘控之相關技術 23
第三章 先前相關架構之研究與技術 33
3.1 基本概念與指標 33
3.1.1 CMOS邏輯電路的開關強度之電流解析度定義 33
3.1.2 電流解析度的改善於MTCMOS 36
3.2 提出具有資料保存之架構 38
3.2.1 第一種ADR-CMOS架構的提出[19] 38
3.2.2 第二種ADR-CMOS架構的提出 39
3.2.3 第三種ADR-CMOS架構的提出[38] 40
3.3 提出ACPG演算法與三種ADRCMOS之改善[7, 19, 39] 41
3.3.1 ACPG演算法的提出 41
3.3.2 設計最佳化睡眠電晶體的尺寸 46
3.3.3 針對Spike與甦醒時間的模擬與分析 48
3.4 第三種ADR-CMOS架構的實現[38] 51
3.4.1 相關電源閘控之低功耗設計的結構比較 52
3.4.2 橋接錯誤分析與植入 53
3.4.3 測試模式之操作定義 56
3.4.4 電流解析度之分析與模擬 57
3.4.5 實體晶片的實現[41] 58
3.5 提出ADR-CMOS結構之SRAM與Address Decoder的應用[42, 43] 62
3.5.1 提出以ADR-CMOS結構之觀念設計的SRAM 62
3.5.2 提出以ADR-CMOS結構之觀念設計的Address Decoder 65
第四章 提出新穎的ADR-CMOS架構 67
4.1 提出新之ADR-CMOS電路架構原理與動作 68
4.2 建立ADR-CMOS邏輯元件庫之設計流程 69
4.2.1 一般IC設計方式 69
4.2.2 提出ADR-CMOS架構之設計流程 71
4.2.3 建立ADR-CMOS架構元件庫之模型與資訊 75
4.3 建立睡眠電流測試架構之程序 81
4.3.1 電源功耗管理架構 81
4.3.2 叢聚架構 81
4.3.3 電流之測試程序 83
4.3.4 IDD電流擾動現象 84
4.4 橋接錯誤的植入與分析 84
第五章 實驗結果 87
5.1 元件庫結構與特性分析 87
5.2 驗證新穎ADR-CMOS架構具有資料保存 88
5.3 新穎ADR-CMOS架構之雜訊邊界分析比較 89
5.4 新穎ADR-CMOS架構之時序分析與比較 90
5.5 新穎ADR-CMOS架構之面積比較 91
5.6 以ISCAS89 Benchmark Circuit之s27電路為例之實驗模擬 92
5.7 使用新穎ADR-CMOS架構之基本元件自動佈局結果 94
5.8 使用ISCAS89 Benchmarks構植入錯誤之模擬 95
第六章 結論 97
参考文獻 98
作者簡歷 103

圖目錄
圖1-1 Moore's Law曲線圖 1
圖1-2 不同製程之漏電流功率與動態功率的比較 3
圖1-3 三種有效降低漏電流的設計方式 4
圖1-4 TSMC Reference Design Flow 6
圖1-5電源閘控於功率管理上產生的電流問題之示意圖 6
圖2-1 互補性與非互補性之CMOS電路示意圖 14
圖2-2 Defect causes high IDDQ 14
圖2-3 The HP test triad[11] 15
圖2-4 製程下降導致好壞電流的變化 16
圖2-5 n-MOS基本結構圖之漏電流路徑 17
圖2-6 製程演進之參數變化 (VDD, VT, IOFF ) (Source: ETW00, Kundu) 18
圖2-7一個電源閘控CMOS電路與其典型尖峰電流 21
圖2-8 (a)內建電流檢測器;(b)各種錯誤之電流分布[24] 22
圖2-9 基塊反相偏壓法 23
圖2-10 實現超閉路開關的方法 24
圖2-11 Fine-與Coarse-grained電源閘控電路 25
圖2-12 電源閘控引起的衝擊 26
圖2-13 以實際的GND檢測短路測試 27
圖2-14 Shannon expansion之分割DUT/CUT測試 28
圖2-15 ZSCCMOS組合電路示意圖 29
圖2-16 ZSCCMOS中的控制電路與低漏電流暫存器 30
圖2-17 (a)提供給電路的輸入強迫器;(b) ZSCCMOS簡化電路 31
圖2-18 新穎特殊的DGPG架構 31
圖3-1 通閉路電流模型 33
圖3-2 (a)兩個反相器與橋接電阻;(b) IDD機率分布圖 34
圖3-3 (a)傳統電路與(b)提出的CMOS電路 35
圖3-4 HVT與LVT元件符號之定義 36
圖3-5 ADR-CMOS元件方塊圖 38
圖3-6 ADR-CMOS1架構圖 39
圖3-7 ADR-CMOS2架構圖 40
圖3-8 ADR-CMOS3架構圖 41
圖3-9 單邊p-type PG結構導通時最大的充電電流和Spike 42
圖3-10 ZSCCMOS 結構之基本原理與配置 43
圖3-11配置的p-n PG開啟時,最小的充電電流與Spike的情況 45
圖3-12 ACPG演算法的執行流程 46
圖3-13 PG結構之睡眠電晶體的等效電路 48
圖3-14 三種ADR-CMOS的配置規格 49
圖3-15 自我調適分散式雙端閘控網路 53
圖3-16 單一橋接電阻於Inverters分析 54
圖3-17 兩組Inverter植入壓控電晶體之映射電路 56
圖3-18 五種電路設計的實現 59
圖3-19 3bits漣波計數器 61
圖3-20 ADR-CMOS3元件實現之佈局 62
圖3-21 14-T與10-T的ADR SRAM cell 63
圖3-22 Butterfly charts of 14-T cells and 10-T cells 64
圖3-23 Proposed LSB-selected data retention address decoder 65
圖4-1 新穎的ADR-CMOS4與ADR-CMOS5之架構圖 67
圖4-2新穎ADR-CMOS5電路架構之動作圖 68
圖4-3 IC Design Methodology 70
圖4-4 ADR-CMOS元件庫設計流程圖 72
圖4-5以反相器為例之Abstract View Generation 74
圖4-6 ADR-CMOS反相器邏輯閘設計 77
圖4-7邏輯資訊描述 78
圖4-8 元件延遲 79
圖4-9 時序限制 80
圖4-10 提出IDDS的測試架構 81
圖4-11提出的叢聚架構 82
圖4-12 電流之測試程序 83
圖4-13 兩個ADR-CMOS架構的反相器電路之說明於橋接錯誤的分析 85
圖5-1 A part of developed standard cells in our cell library. 87
圖5-2 驗證PG與新穎ADR-CMOS結構是否具有資料保存 88
圖5-3 實驗評估新穎ADR-CMOS之靜態雜訊邊界 89
圖5-4 以s27電路為例說明 92
圖5-5 一部分的模擬結果於s27電路 93
圖5-6 使用發展的新穎ADR-CMOS元件庫合成的s420之佈局圖 95


表目錄
表2-1 CMOS ICs測試方法的比較[12] 15
表2-2 漏電流減少的方式之分類 18
表3-1 Predicted on/off currents in ITRS 2000. 37
表3-2 ACPG演算法與ZSCCMOS結構之特定輸入控制向量的比較 48
表3-3 ZSCCMOS與三種ADR-CMOS結構之邊界雜訊與訊號的轉換時間的比較 50
表3-4三種ADR-CMOS結構的Spike與甦醒時間的改善 51
表3-5 主要参考文獻與研究之改善關係表 52
表3-6 單一inverters電路之橋接錯誤測試 54
表3-7測試模式之操作定義 57
表3-8長寬之面積評估與電流解析度的改善 57
表3-9 電流解析度改善之關係表 58
表3-10 Parameters of ADR-CMOS3 Cells 59
表3-11兩個反相器加上橋接錯誤 60
表3-12 64 bits Delay line 加上橋接錯誤 60
表3-13 下線晶片之規格表 61
表3-14 Predicted on/off currents in ITRS 2000 64
表3-15 Current resolution improvements of decoder and SRAM array 66
表3-16 Current resolution improvement of a 8X8 SRAM 66
表4-1 ADR-CMOS反相器之真值表 69
表4-2 Cell List 73
表4-3 ADR-CMOS元件實體規格表 76
表4-4 電器規格表 77
表4-5 Numerical Integration Algorithm Controls 84
表4-6依據圖4-13電路而得的單一橋接錯誤分析 85
表5-1 Static Noise Margin 90
表5-2 HVT、LVT與新穎ADR-CMOS結構之時序模擬比較 90
表5-4 新穎的ADR-CMOS元件之實驗參數 92
表5-5 LVT與新穎ADR-CMOS兩者電路的電流對數表 94
表5-6 ISCAS89 Benchmark Circuits的模擬結果 96
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