臺灣博碩士論文加值系統

本論文提出一個新的低功率電路的設計技術，此技術結合了「非同步電路」與「絕熱邏輯」這兩種低功率技術的優點，稱為「交握式準絕熱邏輯」（Handshaking Quasi-Adiabatic Logic；HQAL）。
HQAL採用dual-rail的資料編碼方式，並且採用非同步交握式方式來傳送資料。因此，HQAL具有非同步電路的優點：沒有時脈歪斜問題、沒有因clock tree所導致的功率消耗，並且在沒有資料輸入時，沒有動態功率消耗。HQAL的邏輯閘的電源是由「交握控制鏈」（Handshake Control Chain）所控制，當HQAL邏輯閘沒有輸入資料時，它得不到電源；只有當HQAL邏輯閘有輸入資料時，它才獲得電源，並且以跟絕熱邏輯相似的方式運作，而達到低功率消耗。利用交握控制鏈，HQAL避免了發生在傳統非同步絕熱邏輯(Asynchronous Adiabatic Logic；AAL)電路裡data token被蓋過的問題。
模擬結果顯示8位元管線Sklansky加法器的HQAL實現方式比傳統CMOS實現方式在輸入資料率為700MHZ的情況下節省了33.1%的功率消耗；在輸入資料率為10MHZ的情況下節省了72.5%的功率消耗。並且在沒有資料輸入的情況下，HQAL裡的絕熱式邏輯區塊不會接到電源，因而HQAL邏輯區塊的漏電流功率消耗相當微小，使得HQAL的實現方式可減少95.6%的靜態功率消耗。

This thesis proposes a novel low-power logic circuit, called handshaking quasi-adiabatic logic (HQAL), which combines the advantages of asynchronous circuits and adiabatic logics.
The HQAL logics adopt dual-rail encoding, and employ handshaking to transfer data between the adjacent modules. Hence, HQAL has the advantages of asynchronous circuits: no clock skew problem, no power dissipation due to the clock tree, and no dynamic power dissipation when there are no input data. The power line of the HQAL logic gates is controlled by the handshake control chain (HCC). A HQAL logic gate is not supplied with power when it has no input data. Only when a HQAL gate has acquired its input data, it can gain the power and then operate in a way similar to the adiabatic logic. Hence, the HQAL logic can achieve low power dissipation. With the handshake control chain, the HQAL circuit can avoid the problem of data token overriding, which may occur in conventional asynchronous adiabatic logic (AAL) circuits.
Simulation results showed that the HQAL implementation of a pipelined Sklansky adder can achieve 33.1% reduction in power dissipation, compared to the CMOS implementation, for a data rate of 700 MHz and 72.5% reduction in power dissipation for a data rate of 10 MHz. Also, the HQAL implementation can achieve up to 95.6% reduction in static power dissipation as the adiabatic logic blocks in HQAL are not powered and have negligible leakage power dissipation when they have no input.

中文摘要......................i
Abstract......................ii
誌謝......................iii
目錄......................iv
圖目錄......................vi
表目錄......................xi
第一章 簡介......................1
1-1 研究背景......................1
1-2 研究動機......................4
1-3 論文結構......................4
第二章 加法器介紹......................5
2-1 全加器（Full Adder）......................5
2-2 漣波進位加法器（Carry-Ripple Adder）.....................6
2-3 前瞻進位加法器（Carry-Lookahead Adder）.................7
2-4 樹狀加法器（Tree Adder）......................10
第三章 常見的低功率電路技術......................17
3-1 Super Cut-off CMOS（SCCMOS）......................17
3-2 Zigzag Super Cut-off CMOS（ZSCCMOS）..................18
3-3 非同步技術的介紹......................20
3-3-1 資料編碼......................20
3-3-1-1 Single-Rail資料編碼......................20
3-3-1-2 Dual-Rail資料編碼......................22
3-3-2 非同步電路的交握協定......................24
3-3-2-1 4-phase交握協定......................24
3-3-2-2 2-phase交握協定......................26
3-3-3 非同步電路的基本元件......................28
3-3-3-1 Muller C-element......................28
3-4 絕熱式邏輯（Adiabatic Logic）的介紹.....................32
3-4-1 絕熱式邏輯的運作原理......................32
3-4-2 Adiabatic Dynamic Logic（ADL）......................34
3-4-3 Efficient Charge Recovery Logic（ECRL）.............36
3-4-4 2N-2N2P Logic......................38
3-4-5 Pass-Transistor Adiabatic Logic（PAL）..............40
第四章 結合非同步技術與絕熱邏輯的相關研究......................43
4-1 Asynchronous, Quasi-Adiabatic (ASYNCHROBATIC) Logic for Low-Power Very Wide Data Width Applications...............43
4-2 Asynchronous Adiabatic Logic......................46
4-3 An Adiabatic Power-Supply Controller for Asynchronous Logic Circuits......................49
第五章 交握式準絕熱邏輯......................52
5-1 交握式準絕熱邏輯的發展原由......................52
5-2 HQAL（1）......................53
5-2-1 HQAL（1）基本架構......................53
5-2-2 HQAL（1）更有效率的設計......................54
5-3 HQAL（2）......................56
5-3-1 HQAL（2）基本架構......................56
5-3-2 HQAL（2）更有效率的設計......................56
第六章 實驗模擬結果......................59
6-1 HQAL（１）模擬分析......................65
第七章 結論......................96
參考文獻......................97
圖2.1 全加器..5
圖2.2 n位元漣波進位加法器..6
圖2.3 四位元的前瞻進位加法器（Carry-Lookahead Adder）..8
圖2.4 四位元的Carry產生器..9
圖2.5 n位元的前瞻進位加法器（Carry-Lookahead Adder）..9
圖2.6 八位元Sklansky樹狀加法器架構圖..12
圖2.7 八位元Sklansky樹狀carry產生器架構圖..12
圖2.8 樹狀加法器cell符號與邏輯圖..13
圖2.9 傳統CMOS邏輯實現的Sklansky樹狀加法器架構圖..13
圖2.10 區塊標示g1的偶數級negative level-sensitive D latch..14
圖2.11 區塊標示g2的奇數級positive level-sensitive D latch..14
圖2.12 區塊標示g3的Carry..14
圖2.13 區塊標示g4的2輸入AND閘..15
圖2.14 區塊標示g5的2輸入XOR閘..15
圖2.15 區塊標示g6的邏輯函式a．b＋c..16
圖3.1 二種SCCMOS架構（a）單一PMOS架構（b）串接兩個PMOS架構[22]..18
圖3.2 二種ZSCCMOS架構（a）當VIN為high的反相器（b）當VIN為low的反相器[23].18 使用ZSCCMOS架構所串接的電路[23]..19
圖3.4 Single-Rail資料編碼..20
圖3.5 Single-Rail功能區塊圖..21
圖3.6 Matched Delay的電路圖..21
圖3.7 Dual-Rail資料編碼..22
圖3.8 n個位元Dual-Rail完成偵測器（a）符號圖（b）邏輯圖..23
圖3.9 （a）在Push Channel的Single-Rail傳輸方式（b）4-phase Single-Rail協定..24
圖3.10（a）在Push Channel的Dual-Rail傳輸方式（b）4-phase Dual-Rail協定..25
圖3.11 操作在Push Channel 的2-phase Single-Rail協定..26
圖3.12（a）2-phase Dual-Rail的2bit Channel傳輸方式（b）使用2-phase的 Dual-Rail協
定的2bit Channel..27
二輸入的Muller C-element（a）符號圖（b）邏輯實現圖（區塊標示為g11）..28
圖3.14 二輸入的Muller C-element的變化類型..29
圖3.15 非對稱式C-element：（a）非對稱式二輸入C-element（b）非對稱式二輸入C-element
（c）非對稱式三輸入C-element..30
圖3.16（a）A CMOS Inverter（b）當in為Low的組態（c）當in為High的組態..32
圖3.17 絕熱式邏輯電阻R的功率消耗示意圖..33
圖3.18（a）ADL反相器（b）Vpc的波形變化和Vout的波形變化（c）串接四級ADL反相
器（d）四相位Vpc的波形變化..34
圖3.19(a）ECRL反相器（b）Vpc的波形變化（c）四相位Vpc的波形變化..36
圖3.20（a）2N-2N2P反相器，區塊標示為g1（b）Vpc的波形變化（c）四相位Vpc的波形
變化..38
圖3.21（a）PAL反相器（b）Vpc的波形變化（c）二相位Vpc的波形變化（d）輸出端點
out的波形變化和輸出端點out_bar的波形變化..40
圖3.22串接PAL四級反相器的實際模擬圖..41
圖4.1（a）Stepwise Charging Circuit（b）Asynchronous Stepwise Charging Controller [18]
..43
圖4.2端點VSW產生類似步階的VSS至VDD波形..44
圖4.3 AAL的區塊圖..46
圖4.4 五種C&R區塊的設計..47
圖4.5 傳輸延遲時間差異性大的AAL管線電路方塊圖..48
圖4.6 AAL管線電路data token被覆蓋(overridden)的地方..48
圖4.7 APSC (Adiabatic Power-Supply Controller) for Asynchronous Logic Circuits [21]..49
vii
圖4.8 充電週期時APSC的波形[21]..50
圖4.9 放電週期時APSC的波形[21]..51
圖5.1 我們提出的HQAL（１）系統區塊圖..53
圖5.2 簡化的HQAL（１）硬體（a）多個絕熱式邏輯閘共用一個C-element（b）使用OR閘
取代完成偵測器..55
圖5.3我們提出的HQAL（２）系統區塊圖..56
圖5.4 簡化的HQAL（２）硬體（a）多個絕熱式邏輯閘共用一個C-element（b）使用OR閘
取代完成偵測器..57
圖5.5使用HQAL（１）設計的八位元管線Sklansky加法器電路圖..58
圖6.1 使用2N-2N2P 邏輯實現的buffer，區塊標示為g2..59
圖6.2 使用2N-2N2P 邏輯實現的二輸入AND閘，區塊標示為g3..60
圖6.3 使用2N-2N2P 邏輯實現的二輸入OR閘，區塊標示為g4..60
圖6.4 使用2N-2N2P 邏輯實現的二輸入XOR閘，區塊標示為g5..61
圖6.5 使用2N-2N2P 邏輯實現的Carry，區塊標示為g6..61
圖6.6 使用2N-2N2P 邏輯實現的Sum，區塊標示為g7..62
圖6.7 使用2N-2N2P 邏輯實現的邏輯函式F＝A⋅B+C，區塊標示為g8..62
圖6.8 使用傳統CMOS邏輯實現的反相器，區塊標示為g9..63
圖6.9 使用傳統CMOS邏輯實現的二輸入OR閘，區塊標示為g10..63
圖6.10 使用傳統CMOS邏輯實現的二輸入Completion Detector，區塊標示為g12..64
圖6.11 八位元五級Sklansky樹狀加法器在輸入資料率每秒700million筆資料的Hspice模
擬圖（a）輸入訊號A0-A7 、輸入訊號B0-B7、進位輸入訊號C0、正向輸出總和訊號S0-S7、反向輸出總和訊號S0-S7以及進位輸出訊號C8；（b）八位元輸入訊號A0-A7；（c）八位元輸入訊號B0-B7和進位輸入訊號C0；（d）八位元輸出訊號S0-S7和進位輸出訊號C8；（e）HCC的C-element輸出訊號；（f）HCC的OR gate輸出訊號；（g）HCC的反相器輸出訊號..68
圖6.12八位元五級Sklansky樹狀加法器在輸入資料率每秒600million筆資料的Hspice模
viii
擬圖（a）輸入訊號A0-A7 、輸入訊號B0-B7、進位輸入訊號C0、正向輸出總和訊號S0-S7、反向輸出總和訊號S0-S7以及進位輸出訊號C8；（b）八位元輸入訊號A0-A7；（c）八位元輸入訊號B0-B7和進位輸入訊號C0；（d）八位元輸出訊號S0-S7和進位輸出訊號C8；（e）HCC的C-element輸出訊號；（f）HCC的OR gate輸出訊號；（g）HCC的反相器輸出訊號..71
圖6.13八位元五級Sklansky樹狀加法器在輸入資料率每秒500million筆資料的Hspice模
擬圖（a）輸入訊號A0-A7 、輸入訊號B0-B7、進位輸入訊號C0、正向輸出總和訊號S0-S7、反向輸出總和訊號S0-S7以及進位輸出訊號C8；（b）八位元輸入訊號A0-A7；（c）八位元輸入訊號B0-B7和進位輸入訊號C0；（d）八位元輸出訊號S0-S7和進位輸出訊號C8；（e）HCC的C-element輸出訊號；（f）HCC的OR gate輸出訊號；（g）HCC的反相器輸出訊號..74
圖6.14八位元五級Sklansky樹狀加法器在輸入資料率每秒400million筆資料的Hspice模
擬圖（a）輸入訊號A0-A7 、輸入訊號B0-B7、進位輸入訊號C0、正向輸出總和訊號S0-S7、反向輸出總和訊號S0-S7以及進位輸出訊號C8；（b）八位元輸入訊號A0-A7；（c）八位元輸入訊號B0-B7和進位輸入訊號C0；（d）八位元輸出訊號S0-S7和進位輸出訊號C8；（e）HCC的C-element輸出訊號；（f）HCC的OR gate輸出訊號；（g）HCC的反相器輸出訊號..77
圖6.15八位元五級Sklansky樹狀加法器在輸入資料率每秒300million筆資料的Hspice模
擬圖（a）輸入訊號A0-A7 、輸入訊號B0-B7、進位輸入訊號C0、正向輸出總和訊號S0-S7、反向輸出總和訊號S0-S7以及進位輸出訊號C8；（b）八位元輸入訊號A0-A7；（c）八位元輸入訊號B0-B7和進位輸入訊號C0；（d）八位元輸出訊號S0-S7和進位輸出訊號C8；（e）HCC的C-element輸出訊號；（f）HCC的OR gate輸出訊號；（g）HCC的反相器輸出訊號..80
圖6.16八位元五級Sklansky樹狀加法器在輸入資料率每秒200million筆資料的Hspice模
擬圖（a）輸入訊號A0-A7 、輸入訊號B0-B7、進位輸入訊號C0、正向輸出總和訊號S0-S7、反向輸出總和訊號S0-S7以及進位輸出訊號C8；（b）八位元輸入訊號
ix
A0-A7；（c）八位元輸入訊號B0-B7和進位輸入訊號C0；（d）八位元輸出訊號S0-S7和進位輸出訊號C8；（e）HCC的C-element輸出訊號；（f）HCC的OR gate輸出訊號；（g）HCC的反相器輸出訊號..83
圖6.17 八位元五級Sklansky樹狀加法器在輸入資料率每秒100million筆資料的Hspice模
擬圖（a）輸入訊號A0-A7 、輸入訊號B0-B7、進位輸入訊號C0、正向輸出總和訊號S0-S7、反向輸出總和訊號S0-S7以及進位輸出訊號C8；（b）八位元輸入訊號A0-A7；（c）八位元輸入訊號B0-B7和進位輸入訊號C0；（d）八位元輸出訊號S0-S7和進位輸出訊號C8；（e）HCC的C-element輸出訊號；（f）HCC的OR gate輸出訊號；（g）HCC的反相器輸出訊號..86
圖6.18八位元五級Sklansky樹狀加法器在輸入資料率每秒50million筆資料的Hspice模
擬圖（a）輸入訊號A0-A7 、輸入訊號B0-B7、進位輸入訊號C0、正向輸出總和訊號S0-S7、反向輸出總和訊號S0-S7以及進位輸出訊號C8；（b）八位元輸入訊號A0-A7；（c）八位元輸入訊號B0-B7和進位輸入訊號C0；（d）八位元輸出訊號S0-S7和進位輸出訊號C8；（e）HCC的C-element輸出訊號；（f）HCC的OR gate輸出訊號；（g）HCC的反相器輸出訊號..89
圖6.19八位元五級Sklansky樹狀加法器在輸入資料率每秒10million筆資料的Hspice模
擬圖（a）輸入訊號A0-A7 、輸入訊號B0-B7、進位輸入訊號C0、正向輸出總和訊號S0-S7、反向輸出總和訊號S0-S7以及進位輸出訊號C8；（b）八位元輸入訊號A0-A7；（c）八位元輸入訊號B0-B7和進位輸入訊號C0；（d）八位元輸出訊號S0-S7和進位輸出訊號C8；（e）HCC的C-element輸出訊號；（f）HCC的OR gate輸出訊號；（g）HCC的反相器輸出訊號..92
表目錄
表2-1 全加器直值表..6
表2-2 各種結構加法器比較表..10
表3-1 Dual-Rail資料編碼真值表..22
表3-2 二輸入的Muller C-element的真值表..28
表6-1 比較以HQAL（１）和傳統CMOS邏輯分別實現的Sum和Carry功能邏輯在不同輸入資料率的平均功率消耗..65
表6-2 比較以HQAL（１）和傳統CMOS邏輯分別設計的八位元Sklansky樹狀加法器在不同輸入資料率的整體電路產生的平均功率消耗..66
表6-3 比較以HQAL（１）和傳統CMOS邏輯分別設計的八位元Sklansky樹狀加法器在不同運作速度上的整體電路因靜態漏電流產生的平均功率消耗..67

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