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研究生:張肇軒
研究生(外文):Zhao-Xuan Zhang
論文名稱:設計與實作面積精簡之先進加密演算法
論文名稱(外文):Design and Implementation of Area-optimized AES Algorithms
指導教授:陳銘志陳銘志引用關係
指導教授(外文):Ming-Chih Chen
學位類別:碩士
校院名稱:國立高雄第一科技大學
系所名稱:電子與資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:108
中文關鍵詞:先進加解密標準演算法積體電路晶片
外文關鍵詞:AESCSEVLSIChip
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在本篇論文裡,我們實現三種不同位元數之先進加密標準(Advanced Encryption Standard,簡稱AES)演算法,包:32 位元、 16 位元及8 位元等三種不同資料路徑寬度的硬體設計。而在AES演算法裡,共有三種流程:加密流程、直接解密流程及改良式解密流程等。在結合加密與解密流程時,一般有兩種方式:加密與直接解密流程結合、加密與改良式解密流程結合。因此,當實現32位元資料路徑寬度的AES演算法時,便有兩種不同的實現方式,而包含16位元及8位元也是。在本論文裡,我們將實現上述所有的架構且與其他文獻所提之結果做比較。
在很多文獻內提到,如何改良AES所需要的電路面積或是運算速度,透過利用不同的架構設計,針對AES部分的轉換函數做化簡以達到節省面積或是利用管線化技術提高其運算能力,而本論文的重點則是著重在如何在不大幅降低其運算能力,可以符合一般嵌入式系統的應用,且可以進一步節省AES的電路面積,使效能與電路面積予以平衡。
在我們的設計裡,對AES的電路面積有兩個改良的方式:第一,是利用架構上的設計,在不犧牲運算的回合數(cycle)下,設計出相關的轉換函數架構;第二,是利用一個共同子運算式化簡(Common Sub-expression Elimination,CSE)演算法來精簡轉換函數內的AND及XOR邏輯閘數目,以達到電路面積更精簡。三種不同位元的架構上和先前的文獻作比較,32位元、16位元及8位元架構確實有達到一個低成本考量的設計,且我們提出的8位元架構設計是以最少運算的cycle數為前提來做低成本設計,其面積和效能比,皆比其他現有的設計更好。
In this dissertation, we realize the Advanced Encryption Standard (AES) algorithm with three kinds of data paths including 32, 16, and 8 bits. There are three kinds of processes in AES algorithm: encryption, direct decryption, and modified decryption. While combining the encryption and decryption processes, two common realization methods are used including the combination of encryption and direct decryption, and the combination of encryption and modified decryption. Therefore, we have two different combination methods in the realization of the 32- or 16- or 8-bit AES designs. In this dissertation, we realize all of the AES architectures mentioned above and compare them with previous designs.
In many previous researches, they discuss how to improve the required circuit area or operation speed of AES design. They also propose different architectures to reduce the area cost of the transformation functions or utilize pipeline technologies to enhance the AES performance with additional area cost. Our dissertation focus on how to reduce the area cost in the AES realization without losing more operation capabilities and how to balance these two design factors: area and performance while applying our designs to embedded systems with restricted resource.
We propose two major methods to improve the area cost in the AES realizations. Firstly, we design the novel architectures in the realization of transformation functions without sacrificing the operation cycles of AES algorithm. Secondly, we design a common sub-expression elimination (CSE) method to further reduce the numbers of XOR and AND gates in the expressions of transformations by extracting more common factors. We observe that our designs have better performance in the ratio of throughput and area compared with previous designs, especially in 8-bit AES design.
中文摘要 1
英文摘要 2
致謝 3
目錄 4
表目錄 6
圖目錄 8
符號說明 11
一. 緒論 12
1.1 動機與目的 12
1.2 研究工具介紹 15
1.3 論文架構 15
二. 文獻探討與回顧 16
2.1 先進加密演算法及研究方向 17
2.2 相關文獻探討 21
三. AES整體設計架構 32
3.1 32位元架構設計 33
3.1.1 加密和直接解密 33
3.1.2 加密和改良式解密 42
3.2 16位元架構設計 46
3.2.1 加密和直接解密 46
3.2.2 加密和改良式解密 52
3.3 8位元架構設計 55
3.3.1 加密和直接解密 55
3.3.2 加密和改良式解密 62
3.4 共同子運算式消減演算法(Common Sub-Expression Elimination) 65四.合成數據結果 69
4.1 32位元加密和直接解密數據 69
4.2 32位元加密和改良式解密數據 72
4.3 16位元加密和直接解密數據 74
4.4 16位元加密和改良式解密數據 76
4.5 8位元加密和直接解密數據 79
4.6 8位元加密和改良式解密數據 81
五. FPGA驗證、晶片實作與比較 84
5.1 FPGA驗證與比較 84
5.2 晶片實作與比較 90
六. 結論與未來展望 100
七. 參考文獻 102
附錄一 107
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