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研究生:蕭文琦
研究生(外文):Wen-Chi Hsiao 
論文名稱:具自我校準功能之互補式金氧半雙斜率時間至數位轉換器之設計與實作
論文名稱(外文):Design and Realization of A CMOS Dual-Slope Time-to-Digital Converter with Self-Calibration
指導教授:陳俊吉陳俊吉引用關係
指導教授(外文):Chun-Chi Chen
學位類別:碩士
校院名稱:國立高雄第一科技大學
系所名稱:電子與資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:104
中文關鍵詞:時間至數位轉換器雙斜率法擴展因子
外文關鍵詞:Time-to-Digital Converter、Dual-Slope
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本論文提出一個無量測範圍限制的具自我校準機制之互補式金氧半雙斜率時間至數位轉換器之設計與實作(TDC),主要原理利用雙斜率法來提高時間量測之解析度,優點在於小面積及可降低環境變異的影響,並借重自我校準的技巧來精準掌控擴展因子的大小,再以簡單之計數器架構來實現自我校準機制以完全克服製程、電壓、溫度變異對有效解析度的影響,進而一步改善電路缺失,也進一步動態地控制電流比率將擴展因子調整到所設計名目值以完成恆定之解析度目標,發展出更高效能及可靠之電路架構。
本電路實現以TSMC 2P4M 0.35μm 製程實現,佈局面積不含輸入/輸出墊(I/O Pad)為0.608mm2、操作頻率則為100MHz,擴展因子為512,是以有效解析度高達19.53ps。
Time-to-Digital Converter (TDC) is the key component for many measurement systems, especially for portable applications. Therefore, the TDC must be integrated to fit the requirements with low-cost, high stability, and high accuracy.
For the demand of achieving the requirements simultaneously, this research improves the operation of the TDC based on dual-slope mechanism. The method using the simple counter scheme focuses on the embedding of self-calibration into the dual-slope TDC to completely overcome the PVT sensitivity of the time resolution. The current ratio of the stretching factor is dynamically adjusted to make the effective stretching ratio fixed. The input pulse will be expanded by the stable stretching factor, and the stretched one is coded by a low frequency reference clock to get the corresponding digital output. The resolution will be greatly enhanced without sacrificing accuracy or power consumption.
The proposed TDC has been implemented in 0.35um standard 2P4M CMOS technology and the layout area is 0.608mm2, excluding the I/O pads. With the 100MHz operation frequency, the effective time resolution is 19.53ps due to the stretching factor is designed as high as 512.
摘 要
Abstract
誌 謝
目 錄
圖目錄
表目錄


第一章 序論
1.1 研究背景 1
1.2 研究動機 2
1.3 章節介紹 4

第二章 時間至數位轉換器 5
2.1 時間至數位轉換器簡介 5
2.2 以計數器法之時間至數位轉換器 6
2.3 游標卡尺法之時間至數位轉換器 8
2.4 現場可程式化閘陣列為主體之時間至數位轉換器 15
2.5 脈衝縮減法之時間至數位轉換器 17
2.5.1 線性脈衝縮減法 17
2.5.2 循環式脈衝縮減法 19
2.5.3 均質與非均質之脈衝縮減延遲線 21
2.6 起始-停止原理之時間至數位轉換器 23
2.6.1 類比至數位轉換器法(A/D) 24
2.6.2 雙斜率法 27

第三章 具自我校準功能之互補式金氧半雙斜率時間至數位轉換器之設計與實作 29
3.1 脈衝擴展法之時間至數位轉換器 30
3.2 具自我校準功能之互補式金氧半雙斜率時間至數位轉換器之設計與實作 33
3.3 時間至脈衝控制電路 34
3.3.1 時間至脈衝控制電路介紹 34
3.3.2 介穩態(Mata-stable state) 37
3.4 脈衝擴展器(Pulse Stretcher,此亦為本電路內插器) 39
3.5 自我校準脈衝擴展器 43
3.5.1 自我校準脈衝擴展器之工作原理 43
3.6 量測脈衝擴展器 45
3.6.1 量測脈衝擴展器之工作原理 45
3.7 脈衝擴展器(內插器)開關切換之誤差 46
3.7.1 電荷注入(Charge injection)問題 46
3.7.2 時脈饋入(Clock Feed-through)問題 48
3.7.3 電容或電晶體漏電 52
3.7.4 放電電容間之寄生耦合電容 53
3.8 比較器 54
3.8.1 比較器之概論 54
3.8.2 比較器之工作原理及特性 55
3.8.3 比較器之架構 59
3.9 計數器 62
3.9.1 N+1 bit校準計數器 63
3.10 充電幫浦 64
3.10.1 充電幫浦之非理想特性 65

第四章 電路模擬與晶片佈局 68
4.1 設計流程與考量 68
4.2 具自我校準功能之互補式金氧化雙斜率時間至數位轉換器模擬結果 71
4.2.1 時間至數位轉換器模擬結果 72
4.2.2 自我校準脈衝擴展器之模擬結果 74
4.2.3 量測脈衝擴展器模擬結果 77
4.2.4 計數器模擬結果 81
4.3 晶片佈局 82

第五章 結論與未來展望 83
5.1 結論 83
5.2 未來研究方向 85


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