臺灣博碩士論文加值系統

在通訊系統中，為了尋找較低的消耗功率、較快的傳輸速度與較小的製作面積，因而衍生出許許多多不同的解決方法，像是改變其編解碼方式、電路製程的改進等等。傳統的通訊架構在電路設計上採用同步式架構的運算方法來實現，但現今於電路上的設計，需求時脈速度的提升、電路設計結構上複雜度的增加，這些需求會導致總體時脈傳輸的延遲、消耗功率過高及電路整合上的時序安排問題，這些問題對同步電路的設計上較難解決，因此在電路設計上會於非同步電路中尋找解決的方法。
傳統的非同步電路在控制電路的設計上，複雜且不易控制，為了降低其複雜度與解決設計上的問題，因此本論文利用狀態機來完成非同步交握協定，並採用同步與非同步混合式架構來完成電路上的實現。
在本論文中，將探討如何將非同步的設計概念套用至同步式渦輪解碼器上，使用免費非同步開發工具Balsa來協助非同步電路上的設計，並將同步與非同步渦輪解碼器用硬體描述語言VHDL來完成電路上的實作，利用Modelsim模擬工具來驗證VHDL運算結果是否正確，最後並於Altera 的Quartus II上做電路面積、消耗功率與速度上的分析與探討。

In communication systems, In order to search for lower power consumption, faster transmission speed and smaller size of the production area, thus derived many of different solutions such as change coding ways, circuit manufacturing process improvements. In the traditional communication systems, the circuit design of the computing architecture is using synchronization method to achieve. However, in today''s circuit design, clock speed of the demand is upgrading, structure of the circuit design complexity increases. These demands will be problems had lead to the overall transmission delay clock, power consumption and high integration of circuits on the scheduling. These issues have implications for the design of synchronous circuits more difficult to solve. Therefore, in the circuit design has to find solutions in asynchronous circuits.
The traditional asynchronous circuit in control circuit design is complex and difficult, in order to reduce the complexity and solve design problems. In this paper, using state machines to complete the asynchronous handshake agreement, and then using synchronous and asynchronous hybrid structure to complete circuits.
In this paper, it will explore how to design the asynchronous circuits based on synchronous circuits and applied to Turbo decoder. Using Balsa development tools to assist asynchronous design. Using VHDL code to implementation Architectures of synchronous and asynchronous Turbo decoder, and then using Modelsim tool to simulation and verify the operation is correct or not. Finally, using Altera''s Quartus II to do the circuit area, power consumption and speed of analysis and discussion.

中文摘要.....................................................................................................i
英文摘要....................................................................................................ii
目錄...........................................................................................................iii
圖目錄.......................................................................................................v
表目錄.....................................................................................................viii
第一章 緒論..............................................................................................1
1.1 簡介.............................................................................................1
1.2 研究動機.....................................................................................2
1.3 論文架構.....................................................................................3
第二章 相關知識與原理..........................................................................4
2.1 非同步架構介紹.........................................................................4
2.2 渦輪碼原理.................................................................................9
2.3 交錯器介紹...............................................................................14
2.4 最大事後機率演算法(MAP)....................................................16
第三章 Balsa軟體應用與設計模擬.....................................................21
3.1 Balsa軟體介紹.........................................................................21
3.2 Balsa軟體模擬與分析.............................................................23
3.3 FPGA模擬與分析...................................................................26
第四章 同步與非同步渦輪解碼器設計模擬........................................30
4.1 非同步渦輪解碼器架構設計...................................................30
4.1.1 同步渦輪解碼器架構介紹..............................................30
4.1.2 非同步渦輪解碼器設計概念..........................................31
4.1.3 MAX*硬體實作................................................................35
4.2 Modelsim模擬.........................................................................36
4.2.1同步渦輪解碼器模擬........................................................36
4.2.2非同步渦輪解碼器模擬....................................................38
4.3 FPGA合成數據分析.................................................................41
4.3.1同步渦輪解碼FPGA合成................................................41
4.3.2非同步渦輪解碼FPGA合成.............................................44
4.3.3同步與非同步渦輪解碼器比較........................................47
4.3.4消耗功率與運算速度分析................................................48
第五章 結論與未來展望........................................................................52
參考文獻..................................................................................................53

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