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研究生:林琮翔
研究生(外文):Tsung-Hsiang Lin
論文名稱:數位控制多相位延遲鎖定迴路使用改良型校準技術
論文名稱(外文):A Digital Controlled Multi-Phase Delay Locked Loop with Calibration Technique
指導教授:陳寶龍陳寶龍引用關係
指導教授(外文):Pao-Lung Chen
學位類別:碩士
校院名稱:國立高雄第一科技大學
系所名稱:電腦與通訊工程所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:133
中文關鍵詞:校準技術延遲鎖定迴路鎖相迴路
外文關鍵詞:calibration techniqueDLLPLL
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本論文提出一種使用數位至電壓轉換器(Digital to Voltage Converter:DVC)之數位控制延遲線,同時設計出數位控的延遲鎖定迴路,利用數位控制與電壓控制延遲線(Voltage controlled delay line)的特點為(1)高解析度的相位延遲,(2)抖動量(jitter)低,(3)製程變異度小的特性,而達到快速鎖定。在傳統的設計當中,電壓控制延遲線通常配合電荷幫浦(Charge Pump)的控制,而此方式的缺點為鎖定速度較慢,因此全數位控制延遲鎖定迴路被提出,但全數位式設計通常有較大的抖動量,本論文中提出一使用數位至電壓轉換器的延遲鎖定迴路,並以此達到低抖動量、快速鎖定的效果。
除此之外,為改善因製程、電壓、溫度(Process, Voltage, Temperature; PVT)所造成的相位偏移,本論文提出一個改良型校準技術,改良了以往以連續式的校準並提高其校準的速度和精確度,以分化而治遞迴的方式做校準的動作,並簡化其電路使之易於實現。
This thesis presents a digital-controlled delay line with digital to voltage converter (DVC) to achieve fast locking. In addition, the digital to voltage converter is applied in a digitally controlled Delay Locked Loop (DLL). The advantages of combining digitally controlled and voltage-controlled delay line characteristics are (1) high-resolution of delay line (2) low jitter (3) low process variation. In conventional design, DLL is usually controlled by a voltage-controlled delay line with the charge pump. The shortcoming of this approach is slow locking time. Therefore, an all-digital controlled delay-locked loop was proposed. However, the jitter is large for all-digital delay locked loop. This thesis proposes a digital to voltage converter to achieve fast locking and low jitter delay locked loop.
In addition, this thesis presents a modified calibration technique in order to improve the phase offset caused by process, voltage, temperature. We improve the traditionally continuous calibration algorithm by divide and conquer. The proposed calibration algorithm simplifies the circuit effort and making it easy to implement.
中文摘要-----------------------------------------------------------------------------------------------I
英文摘要----------------------------------------------------------------------------------------------II
誌謝---------------------------------------------------------------------------------------------------III
目錄---------------------------------------------------------------------------------------------------IV
表目錄------------------------------------------------------------------------------------------------V
圖目錄-----------------------------------------------------------------------------------------------VI
第一章 緒論------------------------------------------------------------------------------------------1
1.1 研究動機--------------------------------------------------------------------------------1
1.2 本論文研究重點-----------------------------------------------------------------------9
1.3 論文章節簡介--------------------------------------------------------------------------9
第二章 傳統延遲鎖定迴路之簡介-------------------------------------------------------------10
2.1延遲鎖定迴路分類-----------------------------------------------------------------10
2.2 延遲鎖定迴路鎖---------------------------------------------------------------------11
2.3傳統延遲鎖定迴路架構簡介-------------------------------------------------------13
2.3.1移位暫存器式延遲鎖定迴路-------------------------------------------------13
2.3.2計數器式延遲鎖定迴路-------------------------------------------------------15
2.3.3連續逼近式延遲鎖定迴路----------------------------------------------------16
2.3.4延遲鎖定迴路使用時間至數位轉換器-------------------------------------18
2.4延遲鎖定迴路發展趨勢-------------------------------------------------------------19
第三章 新型數位控制多相位延遲線----------------------------------------------------------21
3.1新型數位控制多相位延遲線研究-------------------------------------------------21
3.2新型數位控制多相位延遲線設計原理-------------------------------------------21
3.3數位至電壓轉換器-------------------------------------------------------------------22
3.4電壓控制延遲線----------------------------------------------------------------------28
3.5新型數位控制多相-------------------------------------------------------------------32
3.6模擬結果-------------------------------------------------------------------------------33
第四章 數位控制多相位延遲鎖定迴路使用數位至電壓轉換器-------------------------39
4.1 多相位延遲鎖定迴路的介紹------------------------------------------------------39
4.2多相位延遲鎖定迴路的應用-------------------------------------------------------40
4.3數位控制多相位延遲鎖定迴路使用數位轉電壓技術研究-------------------42
4.4數位控制多相位延遲鎖定迴路使用數位轉電壓技術-------------------------43
4.4.1整體架構與設計原理----------------------------------------------------------43
4.4.2鎖定收斂法則分析-------------------------------------------------------------45
4.4.3延遲鎖定迴路電路設計-------------------------------------------------------47
4.4.4延遲鎖定迴路電路模擬結果-------------------------------------------------68
第五章 改良型校準技術-------------------------------------------------------------------------72
5.1多相位輸出偏移現象的介紹-------------------------------------------------------72
5.2各種校準技術的介紹----------------------------------------------------------------75
5.3改良型校準技術事前研究----------------------------------------------------------79
5.4改良型校準技術----------------------------------------------------------------------84
5.4.1改良型校準技術演算法-------------------------------------------------------84
5.4.2改良型校準技術實際實現----------------------------------------------------88
5.4.3校準技術使用Verilog實際模擬---------------------------------------------91
第六章 晶片設計與實現----------------------------------------------------------------99
6.1設計流程-------------------------------------------------------------------------------99
6.2晶片設計與測試考量--------------------------------------------------------------100
6.3 TSMC 0.18 μm 延遲鎖定迴路模擬結果與發表論文比較----------------110
第七章 結論與未來研究方向------------------------------------------------------------------111
7.1結論-----------------------------------------------------------------------------------111
7.2未來研究方向-----------------------------------------------------------------------111
參考文獻-------------------------------------------------------------------------------------------113
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