數位電視節目透過高頻載送播放，在無線數位電視頭端系統中，利用調諧器將高頻信號調變至中頻，使影像與聲音信號能接收下來。類比電視系統採用單轉換中頻輸出，市售產品大多為雙轉換中頻輸出，本論文高頻調諧器以正交本地振盪源單轉換中頻輸出之架構，並針對目前台灣數位電視廣播之頻率範圍530∼596 MHz，做優化設計。
本論文實現之高頻調諧器包含主動式電感放大器、雙平衡主動式混波器及改良式多相位濾波器，整體考量之依據以映像信號排除的比率（Image Rejection Rate；IRR）作為評斷，模擬發現主動式電感放大器提供調諧器極佳增益，此外主動式混波器及改良式多相位濾波器則為排除映像信號之元件，高頻調諧器設計以CMOS元件為考量，有效大幅度降低晶片面積，且藉由ADS模擬其IRR可超過40 dBm與30 dBm的增益，顯示該電路有較佳的效能表現。
最後以TSMC 18μm 1P6M製程實現所設計之高頻調諧器晶片。針對目前台灣已開播的數位電視頻道，其使用頻率範圍530∼596 MHz，整體系統功率增益維持32 dBm以上、映像信號排除率為32 dBm，功率消耗136.7 mW，晶片面積為 0.497 mm2，若映像信號排除率以30 dBm為基準，整體頻率範圍可延伸至602 MHz，晶片均採用CMOS主動式元件設計，有效節省矽晶片面積。

In wireless DTV front-end system, a tuner is to demodulate a high frequency to an intermediate frequency for receive the video and audio in each program. In traditional analog TV used the single conversion with IF output for its easy implementation. In recent years, a double conversion with IF output is used to improve the tuner’s performance. In this thesis, we study a single chip tuner with MOS techniques. The chip includes low noise amplifier （LNA）, RF mixing, digital voltage control oscillator, and polyphase filter. The LNA is designed with an active inductor to reduce the core size and can achieve about 15dBm. The digital voltage control oscillator consists of 5-stage ring oscillator and one 8-bit DAC（Digital to Analog Converter）. We choose a single conversion with IF and Quadrature LO signal by the combination of polyphase filter, and implement by TSMC 0.18μm CMOS process. The frequency band is designed from 530 MHz to 596 MHz for Taiwan DTV channels. The gain of the entire tuner is anout 32 dBm. And the image rejection ratio（IRR）of the tuner is above 30 dBm. The chip had been simulated with ADS tools in success. And the silicon chip is designed with a full custom layout. The chip size and core size is about 0.497 and 0.1095 mm2, respectively. The maximum power dissipation is 136.7 mW when the chip works on the center frequency 566MHz.

中文摘要 ------------------------------------------------------------------------- i
英文摘要 ------------------------------------------------------------------------- ii
誌謝 ------------------------------------------------------------------------------ iii
目錄 ------------------------------------------------------------------------------ iv
表目錄 ------------------------------------------------------------------------- viii
圖目錄 --------------------------------------------------------------------------- ix
第一章 緒論 -------------------------------------------------------------------- 1
1.1 研究動機 ----------------------------------------------------------------- 1
1.2 研究目的 ----------------------------------------------------------------- 2
1.3 數位電視介紹 ----------------------------------------------------------- 4
1.3.1 發展史 -------------------------------------------------------------- 4
1.3.2 簡介 ----------------------------------------------------------------- 5

1.3.3 數位電視標準 ----------------------------------------------------- 7
1.3.4 數位電視的優點 -------------------------------------------------- 9
1.4 電視數位化之未來展望 ----------------------------------------------- 9
1.5 論文架構 --------------------------------------------------------------- 11
第二章 主動式電感基本理論 ---------------------------------------------- 12
2.1 旋相器 ------------------------------------------------------------------ 12
2.2 主動式電感介紹 ------------------------------------------------------ 14
2.2.1 Basic Gyrator-C Active Inductors ------------------------------- 14
2.2.2 Thanachayanont-Payne Cascode Active Inductors ------------ 15
2.2.3 Hsiao Feedback Resistance Cascode Active Inductors ------- 16
2.3 主動式電感相關應用 ------------------------------------------------ 18
2.3.1 主動變壓器（Active Transformers） --------------------------- 18
2.3.2 帶通濾波器（Bandpass Filter） --------------------------------- 21
2.3.3 振盪器（Oscillators） --------------------------------------------- 23
第三章 主動式電感放大器設計與模擬 ---------------------------------- 25
3.1 參數敘述 --------------------------------------------------------------- 25
3.1.1 S參數 --------------------------------------------------------------- 25
3.1.2 靈敏度 ------------------------------------------------------------- 27
3.1.3 雜訊指數 ---------------------------------------------------------- 27
3.1.4 1dB壓縮點 -------------------------------------------------------- 29
3.1.5穩定度 -------------------------------------------------------------- 30
3.1.6輸入三階截斷點 -------------------------------------------------- 32
3.2 主動式電感放大器設計 --------------------------------------------- 33
3.2.1 整體架構 ---------------------------------------------------------- 33
3.2.2 Manetakis Regulated Cascode Active Inductors ------------ 34
3.2.3 負電導（Negative Impedance） --------------------------------- 35
3.3 晶片數據模擬與實現 ------------------------------------------------ 36
3.3.1 S參數模擬 --------------------------------------------------------- 37
3.3.2 雜訊指數（NF） --------------------------------------------------- 38
3.3.3 穩定度（Stability） ------------------------------------------------ 39
3.3.4 1dB線性增益壓縮點（P1dB） ---------------------------------- 40
3.3.5 晶片規格與比較 ------------------------------------------------- 42
第四章 混波器、濾波器與VCO設計與模擬 ---------------------------- 45
4.1 主動式雙平衡混波器 ------------------------------------------------ 45
4.1.1 混波器原理 ------------------------------------------------------- 45
4.1.2 混波器模擬 ------------------------------------------------------- 50
4.2 改良式多相位濾波器 ------------------------------------------------ 53
4.2.1 多相位濾波器原理 ---------------------------------------------- 53
4.2.2 改良式多相位濾波器 ------------------------------------------- 56
4.2.3 模擬結果 ---------------------------------------------------------- 57
4.3 數位型壓控振盪器 --------------------------------------------------- 59
4.3.1 加權式電流數位類比轉換器 ---------------------------------- 59
4.3.2 環型振盪器 ------------------------------------------------------- 62
4.3.3 數位型壓控振盪器模擬 ---------------------------------------- 64
第五章 高頻調諧器設計與模擬 ------------------------------------------- 71
5.1無線數位電視射頻調諧器架構 ------------------------------------- 71
5.2 系統架構 --------------------------------------------------------------- 76
5.3 晶片設計流程 --------------------------------------------------------- 77
5.4 系統模擬與規格 ------------------------------------------------------ 79
第六章 結論與未來展望 ---------------------------------------------------- 85
參考文獻 ----------------------------------------------------------------------- 86

[1]F. Behbahani, Y. Kishigami, J. Leete, A. A. Abidi, “CMOS Mixer and Polyphase Filters for Large Image Rejection,” IEEE JSSC, vol. 36, no. 6, pp.873-887, June 2001.
[2]Chung-Yun Chou, Chung-Yu Wu, “The design of wideband and low-power CMOS active polyphase filter and its application in RF double-quadrature receivers,” IEEE Trans. on Circuits and Systems-I: Regular Papers, vol.52, no.5, pp.825-833, May 2005
[3]F. Tillman, H. Sjöland, “A polyphase filter based on CMOS inverters,” IEEE NORCHIP Conference, 2005.
[4]C. Yue and S. Wong. “On-chip spiral inductors with patterned ground shields for Si-based RF IC”. IEEE J. Solid-State Circuits, 33(5):743–752, May 1998.
[5]C.P. Yue and S.S Wong, “Pyysic modeling of spiral inductors on silicon,” IEEE Trans.on Electron Devices ,vol.47,no.3, pp.560-568, Mar.2000.
[6]S. Hara, T. Tokumitsu and M. Aikawa, “Broad band monolithic microwave active inductors and its application to a miniaturized wide-band amplifier, ” In IEEE Microwave&Millimeter-Wave Monolithic Circuits Symp.Dig., pp.117-120, 1988.
[7]A. Thanachayanont and S. Ngow. “Class AB VHF CMOS active inductor”. In Proc. IEEE Mid-West Symp. Circuits Syst., volume 1, pages 64–67, Aug. 2002.
[8]A. Thanachayanont and A. Payne. “VHF CMOS integrated active inductor”. IEE Electronics Letters, 32(11):999–1000, May 1996.
[9]A. Thanachayanont. “CMOS transistor-only active inductor or IF/RF applications”. In Proc. IEEE Int’l Industrial Tech. Conf., volume 2, pages 1209–1212, Bangkok, 2002.
[10]C. Hsiao, C.Kuo, C. Ho, and Y. Chan. “Improved quality factor of 0.18μm CMOS active inductor by a feedback resistance design”. IEEE Microwave and Wireless Components Letters, 12(2):467–469, Dec. 2002.
[11]C. Wei, H. Chiu, and W. Fend. “An ultra-wideband CMOS VCO with 3-5 GHz tuning range”. In Proc. IEEE Int’lWorkshop Radio-Frequency Integration Tech., pages 87–90, Singapore, Nov. 2005.
[12]R. Mukhopadhyay, Y. Park, P. Sen, N. Srirattana, J. Lee, C. Lee, S. Nuttinck, A. Joseph, J. Cressler, and J. Laskar. “Reconfigurable RFICs in Si-based technologies for a compact intelligent RF front-end”. IEEE Trans. Microwave Theory and Technology, 53(1):81–93, Jan. 2005.
[13]A. Tang, F. Yuan, and E. Law. “A new CMOS BPSK modulator with optimal transaction bandwidth control”. In Proc. IEEE Int’l Symp. Circuits Syst., pages 2550–2553, New Orleans, May 2007.
[14]A. Thanachayanont and A. Payne. “A 3-V RF CMOS bandpass amplifier using an active inductor”. In Proc. IEEE Int’l Symp. Circuits Syst., volume 1, pages 440–443, June 1998.
[15]L. Lu, H. Hsieh, and Y. Liao. “A wide tuning-range CMOS VCO with a differential tunable active inductor”. IEEE Trans. on Microwave Theory Appl., 54(9):3462–3468, Sept. 2006.

[16]Ren-Chieh Liu, Chin-Shen Lin, Kuo-Liang Deng and Huei Wag, “A 0.5-14-GHz 10.6-dB CMOS Cascode Distributed Amplifier,” Symposium on VLSl Circuits Digest of Technical Papers, PP.139-140,2003.
[17]Ran. it Ghqurey, “A Broadband Low-Noise Front-End Amplifier for Ultra Wideband in 0.13 um CMOS,” IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE, PP.605-608, 2004.
[18]Andrea Bevilacqua, and Ali M. Niknejad, “An Ultrawideband CMOS Low-Noise Amplifier for 3.1–10.6-GHz Wireless Receivers,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004.
[19]Chang-Wan Kim, Min-Suk Kang, Phan Tuan Anh, Hoon-Tae Kim, and Sang-Gug Lee, “An Ultra-Wideband CMOS Low Noise Amplifier for 3–5-GHz UWB System,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 2, FEBRUARY 2005.
[20]Frank Zhang and Peter Kinget, “Low Power Programmable-
Gain CMOS Distributed LNA for Ultra-Wideband Applications,” Symposium on VLSI Circuits Digest of Technical Papers, PP.78-81, 2005.
[21]P.R. Gary, P.J. Hurst, S.H. Lewis, R.G. Meyer, “Analysis and design of analog integrated circuits （fourth edition）,” New York: Wiley, 2000.
[22]Guillermo Gonzalez, “Microwave Transistor Amplifiers Analysis and Design,” Englewood Cliffs, N.J. : Prentice-Hall,c1984.
[23]Francesco Gatta, Enrico Sacchi, Francesco Svelto, Paolo Vilmercati, and Rinaldo Castello, “2-dB Noise Figure 900-MHz Differential CMOS LNA, ” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 10, OCTOBER 2001.
[24]Federico Bruccoleri, Eric A. M. Klumperink, and Bram Nauta, “Wide-Band CMOS Low-Noise Amplifier Exploiting Thermal Noise Canceling,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 2, FEBRUARY 2004.
[25]Xiaohua Fan, Heng Zhang, and Edgar Sánchez-Sinencio, “A Noise Reduction and Linearity Improvement Technique for a Differential Cascode LNA,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 3, MARCH 2008.
[26]W. Zhuo, X. Li, S. Shekhar, S. H. K. Embabi, J. Pineda de Gyvez, D. J. Allstot, and E. Sanchez-Sinencio, “A Capacitor Cross-Coupled Common-Gate Low-Noise Amplifier,” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 52, NO. 12, DECEMBER 2005.
[27]楊鎮澤, “The Study of Radio Frequency CMOS Active Inductors and Applications,” 電子研究所, 國立交通大學, 95博士論文.
[28]林冠廷, “無線數位電視中映像信號排除及混波技術之晶片設計,” 電腦與通訊工程研究所, 國立高雄第一科技大學, 96碩士論文.
[29]李文慶, “高速數位類比信號轉換之晶片設計,” 電腦與通訊工程研究所, 國立高雄第一科技大學, 96碩士論文.
[30]李佳展, “CATV的高頻調變技術與晶片設計,” 電腦與通訊工程研究所, 國立高雄第一科技大學, 96碩士論文.
[31]吳思賢, “數位電視調諧器架構技術分析,” 工研院, 系統晶片技術發展中心技術期刊, 第3期, 2005.
[32]M. Notten, J. van Sinderen, F. Seneschal, F. Mounaim, “A low-IF CMOS double quadrature mixer exhibiting 58 dB of image rejection for silicon TV tuners”, in IEEE RFIC Symp. Dig., pp. 171-174, 12-14 June 2005.
[33]M. Wiklund, S. Nilsson, C. Björk, S. Mattisson, “A 2GHz Image-Reject Receiver in A Low IF Architecture Fabricated in A 0.1μm CMOS Technology”, in Proc. IEEE ISCAS, pp. II-161-164, May 2003.