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研究生:蔡瑞隆
研究生(外文):Ruei-Lung tsai
論文名稱:測試資料壓縮基於LFSRreseeding
論文名稱(外文):Test data compression based on LFSR reseeding
指導教授:林義凱林義凱引用關係
指導教授(外文):Yi-Kai Lin
學位類別:碩士
校院名稱:國立屏東教育大學
系所名稱:資訊科學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
畢業學年度:97
語文別:中文
論文頁數:49
中文關鍵詞:seed測試向量LFSR線性方程式
外文關鍵詞:seedtest vectorLFSRlinear equations
相關次數:
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  • 下載下載:20
  • 收藏至我的研究室書目清單書目收藏:0
在論文中,我們使用partial linear feedback shift register(LFSR)去減少測試集合
(test sets)。傳統上,LFSR 架構是利用static LFSR reseeding。額外增加位元是被
用來產生test vector 以減少測試資料數量。方法將產生測試向量經由解線性方程
組,求解出LFSR seed。因此最後的seeds 集合是少於原測試向量。我們分析don’t
care 位元是否影響seed 大小。我們發現當don’t care 位元數量是很小,其seed 的
大小是相對的很小。
這篇論文中,我們提出一個重新排列策略為測試集合中調整don’t care 位元分
佈去增加壓縮率。實驗結果顯示我們提出的方法可以改善壓縮率。
In the thesis, we use the partial linear feedback shift register (LFSR) to reduce
test data volume. Traditionally, LFSR structure is used in static LFSR reseeding. The
additional bit are used to generate the test vector for reducing the amount of test data.
The method generates the test vectors by solving linear equations to reduce the LFSR
seed. Thus the final set of seeds is less than the original test vectors. We analyze the
effect of the don’t care bit to the size of seed. We find that when the number of don’t
care bit is small, the size of seed is relative smaller.
In this thesis, we propose a reorder strategy to adjust the distribution of don’t
care bit in the test set to increase the compression ratio. The results of the work show
that the compression ratio can be improved by the proposed method.
摘 要......................................................................................................................... iii
Abstract ............................................................................................................................. iv
第一章 緒論.................................................................................................................1
第一節 單晶片測試介紹...........................................................................................2
第二節 Test-per-scan架構.........................................................................................3
第三節 Test-per-clock架構.......................................................................................3
第二章 LFSR相關技術...............................................................................................5
第一節 線性方程組與seed介紹...............................................................................5
第二節 LFSR reseeding...........................................................................................11
第三節 Seed overlapping.........................................................................................13
第四節 Partial LFSR reseeding ...............................................................................15
第一小節 Partial LFSR method.......................................................................15
第二小節 Partial LFSR形成和解線性方程組................................................15
第三章 重組test set增進壓縮效率............................................................................18
第一節 test vector reorder...............................................................................18
第二節 test vector中specified bits分佈...................................................................19
第三節 scan window................................................................................................21
第四節 test vector reorder using minimun seed ......................................................23
第五節 交錯式(interleaved)重組............................................................................25
第一小節 策略一test vector中specified bits多搭配少...................................25
第二小節 策略二test vector中specified bits少搭配多...................................30
第四章 實驗結果.......................................................................................................35
第五章 結論與未來研究方向...................................................................................39
Bibliography .....................................................................................................................40
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