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研究生:陳侑廷
研究生(外文):Yu-Ting Chen
論文名稱:鎳化矽/氮化矽複合奈米點的非揮發性記憶體特性研究
論文名稱(外文):Nonvolatile Memory based on NiSi2/SiNX compound nanocrystals
指導教授:朱安國
指導教授(外文):Ann-Kuo Chu
學位類別:碩士
校院名稱:國立中山大學
系所名稱:光電工程研究所
學門:工程學門
學類:材料工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:83
中文關鍵詞:複合鎳化矽
外文關鍵詞:NiSinanocrystalcompound
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目前非揮發性記憶體在元件尺寸持續的微縮下,其需求為高密度記憶單元、低功率損耗、快速讀寫操作以及良好的可靠度(Reliability)。然而傳統浮動閘極(Floating gate)記憶體在操作過程中,穿遂氧化層產生漏電路徑會造成所有儲存電荷流失回到矽基板,隨著尺寸微縮這種情況會更趨嚴重,所以在資料保存時間(Retention)和抗劣化程度(Endurance)的考量下,微縮穿遂氧化層的厚度是非常困難的。具非揮發性奈米點記憶體及SONOS記憶體被提出並希望可取代傳統浮動閘極記憶體,由於彼此分離的儲存點作為儲存中心,所以上述兩者可以有效改善小尺寸記憶體元件多次讀寫操作下的資料儲存能力。
在本論文中,利用改變奈米點的結構與組成來克服傳統非揮發性記憶體在微縮過程中會遭遇到的困難,並更進一步地增加資料保存時間(Retention)。我們首先製作一層鎳化矽薄膜作為鎳矽奈米點的自我析出層(Self-assembled layer),並應用在奈米點非揮發性記憶體上。在室溫環境中,利用分層濺鍍(Sputtering)鎳矽(NiSi2)靶材的方式來形成單層及雙層電荷儲存層,而雙層電荷儲存層又以約30 Å的氧化矽隔開,接著再沉積氧化矽作為控制氧化層(control oxide) ,並經由快速熱退火(RTA)通以氧氣以達到氧化層修補作用且提供鎳化矽足夠熱能使之移動以達最小自由能而形成均勻且高密度的鎳矽奈米點埋藏於氧化層中。由於儲存中心的增加及庫倫斥力的影響,雙層結構之奈米點記憶體記憶窗口和資料保存時間會較單層的鎳矽奈米點有明顯地增加。
同樣地,我們在室溫環境中利用濺鍍鎳矽靶材並通以氬氣與氨氣混氣使之與鎳化矽形成一層氮矽化合物。之後我們同樣經由快速熱退火(RTA)通以氧氣以達到氧化層修補作用及提供鎳化矽足夠動能移動達最小自由能並形成均勻且高密度的奈米點埋藏於氧化層中,而我們藉由TEM、XPS分析可知此奈米點的結構為鎳矽氮/氮化矽複合奈米點。根據後續的電性量測我們更發現鎳矽氮/氮化矽複合奈米點製程相對於傳統鎳奈米點製作,由於介面形成之緻密氮化層使一萬秒後的資料保存時間由原本僅通氬氣的50%提升到72%。甚至相較於僅通氬氣的雙層結構奈米點記憶體68%有更好的資料保存時間。且我們做了一萬次連續寫入抹除的抗劣化性(Endurance)測試實驗中發現,其平帶電壓幾乎沒有受到影響。
故我們可以利用在沈積奈米點儲存層時通以氨氣的方式來達到相同於雙層結構的記憶體特性,以達製成程序簡化的目的。最後,我們所提出的奈米點結構與製造技術都可以應用於非揮發性奈米點記憶體的製程技術同時也適用於現階段積體電路製程。
Current requirements of nonvolatile memory (NVM) are the high density cells, low-power consumption, high-speed operation and good reliability for next-generation NVM application. However, all of the charges stored in the floating gate will leak into the substrate if the tunnel oxide has a leakage path in the conventional NVM during endurance test. Therefore, the tunnel oxide thickness is difficult to scale down in terms of charge retention and endurance characteristics. Nanocrystals (NCs) NVMs are one of the promising candidates to substitute for conventional floating gate memory since the discrete storage nodes as the charge storage media can effectively enable the improvement of data retention for the scaling down device.
In this thesis, we try to overcome the limitation of conventional NVMs during the scaling down process and further increase the retention time by means of changing the structure of Nanocrystals NVMs. Firstly, we deposit a NiSi2 layer as the nanocrystal self-assembled layer and thereby apply it to Nanocrystals NVMs. In room temperature, we bombard NiSi2 target to form single layer and double layer charge trapping layer through sputtering system layer by layer, and the two charge trapping layers are separated by 30 Å silicon-oxide (SiO2). Next, we also deposit silicon oxide as control oxide. According to rapid thermal anneal (RTA) mix oxide gas, we improve the oxide quality and supply NiSi2 sufficient energy to reach the smallest Gibbs free energy so as to form uniform and high density NiSi nanocrystal. On account of the increasing of trapping center and the coulomb repulsion power, the double layer structure NiSi Nanocrystals NVMs has better memory window and retention than the single layer one.
In the similar process, we sputter NiSi2 target with Ar gas mixes NH3 gas to form silicon-nitride compound layers. Then, we use the same RTA process to form nanocrystal and improve the oxide quality. In the light of TEM and XPS analysis, we may infer that the nanocrystal is formed by NiSi2 and SiNX compound. Further, based on our electronic analysis, we can observe that the retention of NiSi2/SiNX compound Nanocrystal NVMs after 104 sec rises from 50% to 72% in comparison with the traditional one due of the quantum well band structure contributes by NiSi2 and SiNX compound nanocrystals. The retention of NiSi2/SiNX compound Nanocrystal NVMs after 104 sec is even better than the double layer without NH3 mixed one, 68%. Furthermore, the threshold voltage of NiSi2/SiNX compound Nanocrystal NVMs has not been subject to change after endurance with 104 programming and erasing cycles continuously.
Thus, by means of depositing nanocrystal charge trapping layer mixed with NH3 gas, we achieve the objective of simplifying the fabrication process. These fabrication techniques for the application of nonvolatile nanocrystal memory can also be applicable to the current manufacture process of the integrated circuit manufacture.
Contents
Chinese Abstract------------------------------------------------------------------I
English Abstract---------------------------------------------------------------III
Acknowledgement------------------------------------------------------------V
Contents-------------------------------------------------------------------------VII
Table Captions-----------------------------------------------------------------IX
Figure Captions---------------------------------------------------------------X
Chapter 1 Introduction
1.1 General Background---------------------------------------------------------------1
1.1.1 SONOS Nonvolatile Memory Devices-------------------------------------3
1.1.2 Nanocrystal Nonvolatile Memory Devices--------------------------------4
1.2 Motivation-------------------------------------------------------------------------10
1.3 Organization of This Thesis-----------------------------------------------------11

Chapter 2 Basic Principles of Nonvolatile Memory
2.1 Introduction------------------------------------------------------------------------14
2.2 Basic Program/Erase Mechanisms----------------------------------------------15
2.2.1 Energy band diagram during program and erase operation-----------15
2.2.2 Carrier injection mechanisms----------------------------------------------16
2.3 Basic Reliability of Nonvolatile Memory--------------------------------------21
2.3.1 Retention--------------------------------------------------------------------.21
2.3.2 Endurance--------------------------------------------------------------------22
2.4 Basic Physical Characteristic of Nanocrystal NVM--------------------------23
2.4.1 Quantum Confinement Effect---------------------------------------------23
2.4.2 Coulomb Blockade Effect--------------------------------------------------23
Chapter 3 Double-layer Nickel-silicide Nanocrystals for Nonvolatile Memory Application
3.1. Introduction------------------------------------------------------------------------35
3.2. Experiment-------------------------------------------------------------------------36
3.3. Results and discussion------------------------------------------------------------37
3.4. Conclusion-------------------------------------------------------------------------38

Chapter 4 Fabrication and Nonvolatile Memory Characteristics of NiSi/SiNX compound NCs (CNCs)
4.1. Introduction------------------------------------------------------------------------45
4.2. Experiment-------------------------------------------------------------------------46
4.3. Results and discussion------------------------------------------------------------47
4.4. Conclusion-------------------------------------------------------------------------48

Chapter 5 Conclusion------------------------------------------------------55
References-----------------------------------------------------------------------57
[1.1] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices”, Bell Syst. Tech, J., 46, 1288 (1967).
[1.2] S. M. Sze, Physics of Semiconductor Devices, Wiley, New York, p. 504 (1981)
[1.3] J. D. Blauwe, “Nanocrystal nonvolatile memory devices”, IEEE Transaction on Nanotechnology, 1, 72 (2002).
[1.4] M. H. White, Y. Yang, A. Purwar, and M. L. French, ”A low voltage SONOS nonvolatile semiconductor memory technology”, IEEE Int’l Nonvolatile Memory Technology Conference, 52 (1996).
[1.5] M. H. White, D. A. Adams, and J. Bu, “On the go with SONOS”, IEEE circuits & devices, 16, 22 (2000).
[1.6] H. E. Maes, J. Witters, and G. Groeseneken, Proc. 17 European Solid State Devices Res. Conf. Bologna 1987, 157 (1988).
[1.7] S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, and D. Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage”, IEEE Int. Electron Devices Meeting Tech. Dig., 521 (1995).
[1.8] J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, and Y. Lee, “Room temperature operation of a quantum-dot flash memory”, IEEE Electron Device Lett., 18, 278 (1997).
[1.9] Y. C. King, T. J. King, and C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si1-xGex”, IEEE Int. Electron Devices Meeting Tech. Dig., 115 (1998).
[1.10] H. A. R. Wegener, A. J. Lincoln, H. C. Pao, M. R. O''Connell, R. E. Oleksiak, “The variable threshold transistor, a new electrically alterable nondestructive read-only storage device,” presented at the Internat''l Electron Devices Meeting, 1967
[1.11] Y. Yang and M. H. Write, “A low voltage SONOS nonvolatile semiconductor memory technology”, IEEE Trans. Comp. Packag., Manufact. Tech., 20, 190 (1997).
[1.12] A. Kanjilal, J. L. Hansen, P. Gaiduk, A. N. Larsen, N. Cherkashin, A. Claverie, P. Normand, E. Kapelanakis, D. Skarlatos, and D. Tsoukalas, “Structural and electrical properties of silicon dioxide layers with embedded germanium nanocrystals grown by molecular beam epitaxy,” Appl. Phys. Lett. 82, 1212 (2003).
[1.13] Y. C. King, T. J. King, and C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si Ge,” IEEE IEDM Tech. Dig., 115-118 (1998).
[1.14] F. K. LeGoues, R. Rosenberg, T. Nguyen, F. Himpsel, and B. S. Meyerson,” Oxidation studies of SiGe” J. Appl. Phys., 65, 1724 (1989).
[1.15] J. Eugene, F. K. LeGoues, V. P. Kesan, S. S. Iyer, and F. M. d’Heurle,” Diffusion versus oxidation rates in silicon-germanium alloys” Appl. Phys. Lett., 59, 78 (1991).
[1.16] V. Craciun, I. W. Boyd, A. H. Reader, and E. W. Vandenhoudt, “Low temperature synthesis of Ge nanocrystals in SiO2,” Appl. Phys. Lett. 65, 3233 (1994).
[1.17] V. Craciun, I. W. Boyd, A. H. Reader, W. J. Kersten, F. J. G. Hakkens, P. H. Oosting, and S. E. W. Vandenhoudt,” Microstructure of oxidized layers formed by the low-temperature ultraviolet-assisted dry oxidation of strained Si0.8Ge0.2 layers on Si” J. Appl. Phys., 75, 1972 (1994).
[1.18] M. Mukhopadhyay, S. K. Ray, C. K. Maiti, D. K. Nayak, and Y. Shiraki,” Properties of SiGe oxides grown in a microwave oxygen plasma” J. Appl. Phys., 78, 6135 (1995).
[1.19] J. M. Madsen, Z. Cui, and C. G. Takoudis,” Low temperature oxidation of SiGe in ozone: Ultrathin oxides” J. Appl. Phys., 87, 2046 (2000).
[1.20] H. K. Liou, P. Mei, U. Gennser, and E. S. Yang,” Effects of Ge concentration on SiGe oxidation behavior” Appl. Phys. Lett., 59, 1200 (1991).
[1.21] F. K. LeGoues, R. Rosenberg, and B. S. Meyerson, ” Dopant redistribution during oxidation of SiGe” Appl. Phys. Lett., 54, 751 (1989).
[1.22] O. Vancauwenberghe, O. C. Hellman, N. Herbots, and W. J. Tan,” New SiGe dielectrics grown at room temperature by low-energy ion beam oxidation and nitridation”, Appl. Phys, Lett., 59, 2031 (1991).
[1.23] C. Tetelin, X. Wallart, J. P. Nys, L. Vescan, and D. J. Gravesteijn, “Kinetics and mechanism of low temperature atomic oxygen-assisted oxidation of SiGe layers”, J. Appl. Phys., 83, 2842 (1998).
[1.24] F. K. LeGoues, R. Rosenberg, and B. S. Meyerson, “Kinetics and mechanism of oxidation of SiGe: dry versus wet oxidation”, Appl. Phys. Lett., 54, 644 (1989).
[1.25] M. Seck, R. A. B. Devine, C. Hernandez, Y. Campidelli, and J. C. Dupuy,” Study of Ge bonding and distribution in plasma oxides of Si1-xGex alloys” Appl. Phys. Lett., 72, 2748 (1998).
[1.26] A. Terrasi, S. Scalese, R. Adorno, E. Ferlito, M. Spadafora, and E. Rimini, ”Rapid thermal oxidation of epitaxial SiGe thin films ” Materials Science and Engineering, B89, 269 (2002).
[1.27] I. G. Kim, H. S. Kim, J. H. Lee, and H. C. Shin,” Silicon nano-crystal. memory with tunneling nitride,”” Ext. Abst. SSDM, 1998, p. 170.
[1.28]I. G. Kim, S. Y. Han, H. S. Kim, J. H. Lee, B. H. Choi, S. W. Hwang, D. Y. Ahn, and H. C. Shin,” Room temperature single electron effects in Si quantum dot memory with oxide-nitride tunneling dielectrics” IEEE Int. Electron Devices Meeting Tech. Dig., 1998, p. 111.
[1.29] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories-part I. Device design and fabrication”, IEEE Trans. Electron Devices, 49, 1606 (2002).
[1.30] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories-part II: electrical characteristics”, IEEE Trans. Electron Devices, 49, 1614 (2002).
[1.31] J De Blauwe, “Nanocrystal nonvolatile memory devices”, IEEE Trans. Nanotechnol, 2002.
[1.32] R. Ohba, N. Sugiyama, K. Uchida, J. Koga, and A. Toriumi, “Nonvolatile Si quantum memory with self-aligned doubly-stacked dots”, IEEE Trans. Electron Devices 49, 1392 (2002).
[1.33] Y. C. King, T. J. King, and C. Hu, “Charge-trap memory device fabricated by oxidation of Si1-xGex”, IEEE Trans. Electron Devices 48, 696 (2001)
[1.34] Y. Shi et al., in Proceedings of the First Joint Symposium on Opto- and Microelectronic Devices and Circuits, 2000, pp. 142–145.
[1.35] H. G. Yang, Y. Shi, S. L. Gu, B. Shen, P. Han, R. Zhang, and Y. D. Zhang, “Numerical investigation of characteristics of p-channel Ge/Si hetero-nanocrystal memory”, Microelectron. J., 34, 71 (2003).
[1.36] Zengtao Liu, Chungho Lee, Venkat Narayanan, Gen Pei, and Edwin Chihchuan Kan, “Metal Nanocrystal Memories—Part I: Device Design and Fabrication”, IEEE Trans. Electron Devices, VOL. 49, NO. 9, SEPTEMBER 2002.
[1.37] Chungho Lee, Udayan Ganguly, Venkat Narayanan, and Tuo-Hung Hou, “Asymmetric Electric Field Enhancement in Nanocrystal Memories”, IEEE Eelectron Electron Letters, vol. 26, NO. 12, DECEMBER 2005.
[1.38] Jong Jin Leea, Yoshinao Harada Jung, Woo Pyun, and Dim-Lee Kwong “Nickel nanocrystal formation on HfO2 dielectric for nonvolatile memory device applications”, Applied Physics Letters 86, 103505 (2005)
[1.39] W. R. Chen, T. C. Chang, P. T. Liu, P. S. Lin, C. H. Tu, and C. Y. Chang “Formation of stacked Ni silicide nanocrystals for nonvolatile memory application”, Applied Physics Letters 90, 112108 (2007)
[1.40] S. K. Samanta, Won Jong Yoo, and Ganesh Samudra, “Tungsten nanocrystals embedded in high-k materials for memory application”, Applied Physics Letters , 87, 113110 (2005)
[1.41] S. K. Samanta, P. K. Singh, Won Jong Yoo, Ganesh Samudra, and Yee-Chia Yeo, “Enhancement of Memory Window in Short Channel Non-Volatile Memory Devices Using Double Layer Tungsten Nanocrystals”, IEEE Electron Device Letter, (2005)
[1.42]Shan Tang, Chuanbin Mao, Yueran Liu, and Sanjay K. Banerjee “Protein-Mediated Nanocrystal Assembly for Flash Memory Fabrication”, IEEE Trans. on Electron Letters, vol. 54, no. 3, March 2007.
[1.43] L. Guo, E. Leobandung, and S. Y. Chou, “Si single-electron MOS memory with nanoscale floating-gate and narrow channel,” in Int. Electron Devices Meeting Tech. Dig., 1996, pp. 955–956.
[1.44] Y. H. Lin, C. H. Chien, C. T. Lin, C. W. Chen, C. Y. Chang, and T. F. Lei, “High performance multi-bit nonvolatile HfO/sub 2/ nanocrystal memory using spinodal phase separation of hafnium silicate”, in Int. Electron Devices Meeting Tech. Dig., 2004, pp. 1080–1082.
[1.45] S. M. Yang, J. J. Huang, C. H. Chien, P. J. Taeng, L. S. Lee, M. J. Tsai, and T. F. Lei, “High Charge Storage Characteristics of CeO2 Nanocrystals for Novolatile Memory Applications”, in Int. Electron Devices Meeting Tech. Dig., 2008, pp. 48–49.
[1.46] N. Takahashi, H. Ishikuro, and T. Hiramoto, “A directional current switch using silicon electron transistors controlled by charge injection into silicon nano-crystal floating dots,” in Int. Electron Devices Meeting Tech. Dig., 1999, pp. 371–374.
[1.47] J. Wahl, H. Silva, A. Gokirmak, A. Kumar, J. J. Welser, and S. Tiwari, “Write, erase and storage times in nanocrystal memories and the role of interface states,” in Int. Electron Devices Meeting Tech. Dig., 1999, pp. 375–378.
[1.48] T.Y.Chan, K.K.Young and C.Hu, “A true single-transistor oxide- nitride-oxide EEPROM device”. IEEE Electron Device Letters, vol.8, no.3, pp.93-95, 1987.
[1.49] “International Technology Roadmap for Semiconductors, 2007 update” at http://public.itrs.net/Files/2007Update/Home.pdf.
[2.1] Chih-Yuan and Chin-Chieh Yeh, “Advenced Non-Volatile Memory Devices with Nano-Technology”, Invited Talk for 15th International Conference on Ion Implantation Technology, 2004.
[2.2] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, Proceedings of The IEEE, 85, 1248 (1997)
[2.3] M. Woods, Nonvolatile Semiconductor Memories: Technologies, Design, and Application, C. Hu, Ed. New York: IEEE Press, (1991) ch. 3, p.59.
[2.4] T. Ohnakado, H. Onoda, O. Sakamoto, K. Hayashi, N. Nishioka, H. Takada, K. Sugahara, N. Ajika and S. Satoh, “Device characteristics of 0.35 m P-channel DINOR flash memory using band-to-band tunneling-induced hot electron (BBHE) programming”, IEEE Trans. Electron Devices, Vol. 46, pp. 1866-1871, 1999.
[2.5] J. Bu, M. H. White, Solid-State Electronics., 45, 113 (2001)
[2.6] M. L. French, M. H. White., Solid-State Electron., p.1913 (1995)
[2.7] M. L. French, C. Y. Chen, H. Sathianathan, M. H. White., IEEE Trans Comp Pack and Manu Tech part A., 17, 390 (1994)
[2.8] Y. S. Hisamune, K. Kanamori, T. Kubota, Y. Suzuki, M. Tsukiji, E. Hasegawa, A. Ishitani, and T. Okazawa, IEDM Tech. Dig., p.19 (1993)
[2.9] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, IEEE Transactions of
Electron Devices., 49, 1606 (2002)
[2.10] J. Moll, Physics of Semiconductors. New York: McGraw-Hill, (1964)
[2.11] M. Lezlinger and E. H. Snow, J. Appl. Phys., 40, 278 (1969)
[2.12] Christer Sevensson and Ingemar Lundstrom, J. Appl. Phys., 44, 4657 (1973)
[2.13] P. E. Cottrell, R. R. Troutman, and T. H. Ning, IEEE J. Solid-State Circuits, 14, 442 (1979)
[2.14] C. Hu, IEDM Tech. Dig., p.22. (1979)
[2.15] S. Tam, P. K. Ko, C. Hu, and R. Muller, IEEE Trans. Elec. Dev., 29, 1740 (1982)
[2.16] I. C. Chen, C. Kaya, and J. Paterson, IEDM Tech. Dig., p.263 (1989)
[2.17] I. C Chen, D. J. Coleman, and C. W. Teng, IEEE Elec. Dev. Lett., 10, 297 (1989)
[2.18] T. Ohnakado, K. Mitsunaga, M. Nunoshita, H. Onoda, K. Sakakibara, N. Tsuji, N. Ajika, M. Hatanaka and H. Miyoshi, IEDM Tech. Dig., p.279 (1995)
[2.19] Suk-Kang Sung, I1-Han Park, Chang Ju Lee, Yong Kyu Lee, Jong Duk Lee, Byung-Gook Park, Soo Doo Chae, and Chung Woo Kim, ”Fabrication and Program/Erase Characteristics of 30-nm SONOS Nonvolatile Memory Devices, ” IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL.2, NO.4, DECEMBER 2003.
[2.20] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, Proceedings of The IEEE, 85, 1248 (1997)
[2.21] D. Ielmini, A. Spinelli, A. Lacaita, and A. Modelli, “Statistical model of reliability and scaling projections for Flash memories,” in IEDM Tech. Dig., 2001, pp.32.2.1–32.2.4.
[2.22] D. Ielmini, A. S. Spinelli, A. L. Lacaita, L. Confalonieri, and A. Visconti,“New technique for fast characterization of SILC distribution in Flash arrays,” in Proc. IRPS, 2001, pp. 73–80.
[2.23] D. Ielmini, A. S. Spinelli, A. L. Lacaita, R. Leone, and A. Visconti, “Localization of SILC in Flash memories after program/erase cycling,” in Proc. IRPS, 2002, pp. 1–6.[2.24] Y. M. Niquet, G. Allan, C. Delerue and M. Lannoo, “Quantum confinement in germanium nanocrystals,” Applied Physics Letters, vol.77, pp.1182-1184 (2000)
[2.25] T. Takagahara and K.Takeda, “Theory of the quantum confinement effect on excitons in quantum dots of indirect- gap materials,” Phys. Rev. B, Vol. 46, p. 15578, 1992.
[2.26] J.D.Jackson, “Classcial Electrodynamics”, published by John Wiley & Sons, 1999.
[3.1] C. Lee, U. Ganguly, V. Narayanan, and T. H. Hou, “Asymmetric Electric Field Enhancement in Nanocrystal Memories”, IEEE Eelectron Electron Letters, 26, 12, (2005).
[3.2] J. D. Blauwe, “Nanocrystal nonvolatile memory devices”, IEEE Trans. on nanotechnology, 1, pp. 72-77 (2002)
[3.3] W. R. Chen, T. C. Chang, P. T. Liu, P. S. Lin, C. H. Tu, and C. Y. Chang, “Formation of stacked Ni silicide nanocrystals for nonvolatile memory application”, Appl. Phys. Lett., 90, 112108 (2007)
[3.4] M. Shalchian, J. Grisolia, G. Ben Assayag, H. Coffin, S. M. Atarodi, and A. Claverie, “Room-temperature quantum effect in silicon nanoparticles obtained by low-energy ion implantation and embedded in a nanometer scale capacitor” Appl. Phys. Lett., 86, 163111 (2005).
[3.5] W. Guan, S. Long, Q. Liu, Y. Hu, Z. Li, and R. Jia, “Modeling of retention characteristics for metal and semiconductor nanocrystal memories”, Solid-State Electronics, 51, pp. 806-811 (2007)
[3.7] C. Y. Ng, T. P. Chen, L. Ding, S. Fung, “Impact of programming mechanisms on the performance and reliability of nonvolatile memory devices based on Si nanocrystals”, IEEE Electron Device Lett., 27, pp. 231- 233 (2006)
[3.9] D. R. Lide, CRC Handbook of Chemistry and Physics, 81st ed. (CRC,Boca Raton, FL, 2000), Vol. 81, p. 5-3.
[3.10] M. C. Poon, C. H. Ho, F. Deng, S. S. Lau, and H. Wong, “Thermal stability of cobalt and nickel silicides”, Microelectronics Reliability, 38 pp. 1495-1498 (1998)
[3.11] W. R. Chen, T. C. Chang, P. T. Liu, C. H. Tu, F. W. Chi, S. W. Tsao, and C. Y. Chang, “Formation of stacked nickel-silicide nanocrystals by using a co-mixed target for nonvolatile memory application”, Surface & Coatings Technology, 202 pp. 1292–1296 (2007)
[3.12] T. C. Chang, S. T. Yan, P. T. Liu, C. H. Hsu, M. T. Tang , S. M. Sze, “A distributed charge storage with GeO nanodots”, Appl. Phys. Lett., 84, p.2581 (2004)
[3.13] S. K. Samanta, P. K. Singh, Won Jong Yoo, G. Samudra1,Yee-Chia Yeo, L. K. Bera, and N. Balasubramanian, “Enhancement of Memory Window in Short Channel Non-Volatile Memory Devices Using Double Layer Tungsten Nanocrystals”, in IEDM Tech. Dig., pp. 170-173 (2005)
[3.14 ]Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories. I. Device design and fabrication”, IEEE Trans. Electron Devices, vol. 49, pp. 1606- 1613 (2002)
[3.15] T. Takagahara, and K.Takeda, “Theory of the quantum confinement effect on excitons in quantum dots of indirect-gap materials”, Phys. Rev. B, Vol. 46, p. 15578, (1992)
[4.1] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to flash memory”, Proceedings of the IEEE 91, 4 (2003).
[4.2] J. D. Blauwe, “Nanocrystal nonvolatile memory devices”, IEEE Trans. Nanotechnol. 1, 72 (2002).
[4.3] C. Y. Lu, T. C. Lu, and R. Liu, “Non-Volatile Memory Technology-Today and Tomorrow”, Proceedings of 13th IPFA (2006).
[4.4] S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, and D. Buchanan, “Volatile and non-volatile memories in silicon with nano-crystalstorage”, IEDM Tech. Dig. 521 (1995).
[4.5] J. H. Jung, J. Y. Jin, I. Lee, T. W. Kim, H. G. Roh, and Y. H. Kim, “Memory effect of ZnO nanocrystals embedded in an insulating polyimide layer”, Appl. Phys. Lett., 88, 112107 (2006).
[4.6] C. Lee, T. H. Hou, and E. C. C. Kan, “Nonvolatile memory with a metal nanocrystal/nitride heterogeneous floating-gate”, IEEE Trans. Electron Devices, 52, 2697 (2005).
[4.7] W. R. Chen, T. C. Chang, P. T. Liu, J. L. Yeh, C. H. Tu, J. C. Lou, C. F. Yeh, and C. Y. Chang, “Nonvolatile memory characteristics of nickel-silicon-nitride nanocrystal “Appl. Phys. Lett., 91, 082103 (2007).
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