|
Reference [1.1] W. E. Howard, “Thin Film Transistors,” edited by C. R. Kagan and P. Andry (Dekker, New York, 2003), pp.1. [1.2]H. Oshima and S. Morozumi, “Future trends for TFT integrated circuits on glass substrates,” IEDM Tech. Dig., 157, 1989 [1.3] S. Zhang, C. Zhu, J. K. O. Sin, J. N. Li, and P. K. T. Mok, “Ultra-Thin Elevated Channel Poly-Si TFT Technology for Fully-Integrated AMLCD System on Glass,” IEEE Trans. Electron Devices, Vol. 47, No. 3, pp. 569–575, March 2000. [1.4] Z. Meng, M. Wang, and M. Wong, “High Performance Low Temperature Metal-Induced Unilaterally Crystallized Polycrystalline Silicon Thin Film Transistors for System-on-Panel Applications,” IEEE Trans. Electron Devices, Vol. 47, No. 2, pp. 404–409, February 2000. [1.5] S. D. S. Malhi, H. Shichijo, S. K. Banerjee, R. Sundaresan, M. Elahy, G. P. Pollack, W. F. Richardson, A. H. Shah, L. R. Hite, R. H. Womack, P. K. Chatterjee, and H. W. Lam, “Characteristics and Three-Dimensional Integration of MOSFET’s in Small-Grain LPCVD Polycrystalline Silicon, ”IEEE Solid-State Circuits, Vol.SC-20, No.1, pp.178-201, Feb. 1985. [1.6] H. Kuriyama et al., “An asymmetric memory cell using a C-TFT for ULSI SRAM,” Symp. On VLSI Tech., p.38, 1992 [1.7] T. Yamanaka, T. Hashimoto, N. Hasegawa, T. Tanala, N. Hashimoto, A. Shimizu, N. Ohki, K. Ishibashi, K. Sasaki, T. Nishida, T. Mine, E. Takeda, and T. Nagano, “Advanced TFT SRAM cell technology using a phase-shift lithography,” IEEE Trans. Electron Devices, Vol. 42, pp.1305-1313,1995. [1.8]Shunji Seki, Osamu Kogure, and Bunjiro Tsujiyama, “Effects of Crystallization on trap State Densities at Grain Boundaries in Polycrystalline Silicon”, IEEE Electron Device Lett., vol.8, pp.368-370, August 1987. [1.9]T. W. Little, K. I. Takahara, H. Koike, et al, “Low Temperature Poly-Si TFTs Using Solid Phase Crystallization of Very Thin Films and an Electron Cyclotron Resonance Chemical vapor deposition gate insulator”, Jpn. J. Appl., Phys., vol.30, no.12B, pp.3724-3728,December 1991. [1.10]Hiroyuki Kuriyama, Seiichi Kiyama, Shigeru Nouguchi, et al, “Enlargement of poly-Si Film Grain Size by Excimer Laser Annealing and its Application to High-Performance Poly-Si Thin Film Transistor”, Jpn. J. Appl. Phys., vol.30, no.12B, pp.3700-3703, December 1991. [1.11]S. W. Lee and S.K. Joo, “Low Temperature Poly-Si Thin Film Transistors Fabrication by Metal-Induced Lateral Crystallization”, IEEE Electron Device Lett., vol.17, no4,pp.160-162, April 1996. [1.12]J. B. Boyce and P. Mei, “Laser crystallization for polycrystalline silicon device applications,” in Technology and Application of Amorphous Silicon, R. A. Street, Ed. New York: Springer-Verlag, pp.94-146, 2000. [1.13]J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider, “Conductivity behavior in polycrystalline semiconductor thin film transistors,” J. Appl. Phys. Vol. 53, pp.1193-1202, 1982. [1.14]P. Migliorato, C. Reita, G. Tallarida, M. Quinn and G. Fortunato,”Anomalous Off-Current Mechanisms in N-Channel Poly-Si Thin Film Transistors.” Solid-State-Electronics, Vol.38, No.12, pp.2075-2079, 1995. [1.15]M. Hack, I-W. Wu, T. J. King and A. G. Lewis, “Analysis of Leakage Currents in Poly-silicon Thin Film Transistors,”IEDM Tech Dig., Vol. 93, pp.385-388,December 1993. [1.16]K. Ono, T. Aoyama, N. Konishi, and K. Miyata, “Analysis of Current-Voltage Characteristics of Low-Temperature-Processed Polysilicon Thin-Film Transistors,” IEEE Trans. Electron Devices, Vol. 39, No. 4, pp. 792-802, April 1992. [1.17]A. Rodriguez, E. G. Moreno, H. Pattyn, J. F. Nijs, and R. P. Mertens, “Model for the Anomalous Off-Current of Polysilicon Thin-Film Transistors and Diodes” IEEE Trans. Electron Devices, Vol. 40, No. 5, pp.938-943, May 1993. [1.18]K. Y. Choi and M. K. Han, “A Novel Gate-Overlapped LDD Poly-Si Thin-Film Transistor,” IEEE Electron Device Lett., Vol. 17, No. 12, pp. 566-568, December 1996. [1.19]M. Valdinoci, L. Colalongo, G. Baccarani, G. Foutunato, A. Pecora, and I. Policicchio, “Floating body effects in polysilicon thin-film transistors,” IEEE Trans. Electron Devices, Vol.44, pp.2234-2241, 1997. [1.20]T. I. Kamins and Marcoux, “Hydrogenation of Transistors Fabricated in Polycrystalline-Silicon Films,” IEEE Electron Devices Lett., Vol. EDL-1, No. 8, pp. 159-161, August 1980. [1.21]B. A. Khan and R. Pandya, “Activation Energy of Source-Drain Current in Hydrogenated and Unhydrogenated Polysilicon Thin-Film Transistors,” IEEE Trans. Electron Devices, Vol. 37, No. 7, pp.1727-1734, July 1990. [1.22]K. Baert, H. Murai, K. Kobayashi, H. Namizaki, and M. Nunoshita, “Hydrogen Passivation of Polysilicon Thin-Film Transistors by Electron-Cyclotron-Resonance Plasma,” Jpn. J. Appl. Phys., Vol. 32, No. 6A, pp. 2601-2606, June 1993. [1.23] T. Aoyama, K. Ogawa,Y. Mochizuki, and N.Konishi, “Inverse staggered poly-Si and amorphous Si double structure TFT''s for LCD panels with peripheral driver circuits integration,” IEEE Trans. Elec. Dev., 43, pp. 701 (1996) [1.24] K. Yoneda, R. Yokoyama, and T. Yamada, “Development trends of LTPS TFT LCDs for mobile applications,” in Proc. Symp. VLSI Circuits, pp. 85–90 (2001). [1.25] H. Tokioka, M. Agari, M. Inoue, T. Yamamoto, H. Murai, and H. Nagata, “Low power consumption TFT-LCD with dynamic memory embedded in pixels,” in Proc. SID, pp. 280–283 (2001). [1.26] C. Y. Chen, J. W. Lee, M. W. Ma, W. C. Chen, H. Y. Lin, K. L. Yeh, S. D. Wang, and T. F. Lei, “Bias temperature instabilities for low-temperature polycrystalline silicon complementary thin-film transistors,” J. Electrochem. Soc., 154, H704-707, 2007 [1.27] Chih-Yang Chen, Jam-Wem Lee, Shen-De Wang, Ming-Shan Shieh, Po-Hao Lee, Wei-Cheng Chen, Hsiao-Yi Lin, Kuan-Lin Yeh, and Tan-Fu Lei “Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors” IEEE Trans. Elec. Dev., 53, pp. 2993-3000, 2006. [1.28] S. Ogawa and N. Shiono, “Generalized diffusion-reaction model for the low-field charge-buildup instability at the Si−SiO2 interface,” Phys. Rev. B, Condens. Matter, 51, pp. 4218–4230, 1995. [1.29] S. Hashimoto, Y. Uraoka, T. Fuyuki, and Y. Morita, “Analysis of thermal distribution in low- temperature polycrystalline silicon p-channel thin film transistors,” Jpn. J. Appl. Phys., 45, pp. 7-12, 2006. [1.30]T. Yamanaka, T. Hashimoto, N. Hashimoto, T. Nishida, A. Shimizu, K. Ishibashi, Y. Sakai, K. Shimohigashi,and E. Takeda,”A 25-u,new poly-Si PMOS load(PPL) SRAM cell having excellent soft error immunity,” in IEDM Tech. Dig.,1988,p.48. [1.31]E. H. Nicollian and J. R. Brews,MOS Physics and Technology(Wiley-Interscience,New York,1982),pp.794-798. [1.32]B. E. Deal,M. Sklar,A. S. Grove,and E. H. Snow,J. Electrochem.Soc.114,267(1967). [1.33]A.Goetzberger,A.D.Lopez,andR.J.Strain,J. Electrochem.Soc.120,90(1973). [1.34]M. Nakagiri,Jpn. J. Appl. Phys. 13,1619(1974). [1.35]K. O. Jeppson and C. M. Svensson, J. Appl. Phys.48,2004(1977). [1.36]A. K. Sinha and T. E. Smith,J. Electrochem. Soc.125,743(1978). [1.37]L. Risch, in Insulating Films on Semiconductors, edited by M. Schulz and G. Pensl(Springer,Berlin,1981),p.39. [1.38]S. Maeda, S. Maegawa, T. Ipposhi, H. Nishimura, T. Ichiki, J. Mitsuhashi, M. Ashida, T. Muragishi, and T. Nishimura,”Negative-bias temperature instability in poly-Si TFT’s,” in Tech. Dig. Symp. VLSI Technol.,1993,p.29. [1.39]S. Maeda, S. Maegawa, T. Ipposhi, H. Nishimura, T. Ichiki, J. Mitsuhashi, M. Ashida, T. Muragishi, Y. Inoue,and T. Nishimura,”Mechanism of negative-bias temperature instability in polycrystalline-silicon thin-film transistors,”J. Appl. Phys.,vol. 76,p.8160,1994. [1.40]M. Makabe, T. Kubota, and T. Kitano, IEEE Int. Reliability Phys. Symp.38,205(2000). [1.41]V. Reddy,A. T. Krishnan,A. Marshall,J. Rodriguez,S. Natarajan,T. Rost,and S. Krishnan,IEEE Int. Rel. Symp. 40, 248 (2002). [1.42]C. Y. Chen, J. W. Lee, S. D. Wang, M. S. Shieh, P. H. Lee, W. C. Chen, H. Y. Lin, K. L. Yeh, and T. F. Lei, “Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors,” IEEE Trans. Electron Devices, Vol. 53, No. 12, pp. 2993–3000, December 2006. [1.43]I. W. Wu, W. B. Jackson, T. Y. Huang, A. G. Lewis, and A. Chiang, “Mechanism of Device Degradation in n- and p-Channel Polysilicon TFT’s by Electrical Stressing,” IEEE Electron Device Lett., Vol. 11, No. 4, pp. 167–170, April 1990. [1.44]C. E. Blat, E. H. Nicollian, and E. H. Poindexter, “Mechanism of Negative Bias-Temperature Instability,” J. Appl. Phys., Vol. 69, No. 3, pp. 1712–1720, February 1991. Reference [2.1] C. Prat, D. Zahorski, Y. Helen, T. M. Brahim, and O. Bonnaud. “Excimer laser annealing system for AMLCDs: a long laser pulse for high performance, uniform and stable TFT.” SPIE Proceedings, Vol.4295,p. 33 (2001). [1.2]H. Oshima and S. Morozumi, “Future trends for TFT integrated circuits on glass substrates,” IEDM Tech. Dig., 157, 1989. [2.2]G.-Y. Yang, S,-H. Hur, and C.-H Han, “A Physical-Based Analytical Turn-On Model of Polysilicon Thin-Film Transistors for Circuie Simulation,” IEEE Trans. Electron Devices, 46(1), 165-172 (1999). [2.3]Ted Kamins, “Polycrystalline silicon for integrated circuits and displays”,second edition. [2.4]H. Chern, C. Lee, and T. Lei, “Correlation of polysilicon thin filmtransistor characteristics to defect states via thermal annealing,” IEEE Trans. Electron Devices, vol. 41, p. 460, 1994. [2.5] N. Lifshitz and S. Luryi, “Enhanced channel mobility in polysiliconthin film transistors,” IEEE Electron Device Lett., vol. 15, p. 274,1994. [2.6] D. K. Schroder, “Semiconductor Material and Device Characterization, 2nd ed, New York: Wiley, 1998. [2.7] G.-Y. Yang, S,-H. Hur, and C.-H Han, “A Physical-Based Analytical Turn-On Model of Polysilicon Thin-Film Transistors for Circuie Simulation,” IEEE Trans. Electron Devices, 46(1), 165-172 (1999). [2.8]J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider, “Conductivity behavior in polycrystalline semiconductor thin film transistors,” J. Appl. Phys. Vol. 53, pp.1193-1202, 1982 [2.9] P. Migliorato, C. Reita, G. Tallatida, M. Quinn and G. Fortunato,40 “Anomalous off-current mechanisms in n-channel poly-Si thin film transistors.” Solid-State-Electronics, Vol.38, pp.2075-2079, 1995 [2.10]M. Hack, I-W. Wu, T. H. King and A. G. Lewis, “Analysis of Leakage Currents in Poly-silicon Thin Film Transistors,” IEDM Tech. Dig., vol. 93, pp. 385-387, 1993 [2.11]N. Kubo, N. Kusumoto, T. Inushima, and S. Yamazaki, “Characteristics of polycrystalline-Si thin film transistors fabricated by excimer laser annealing method,” IEEE Trans. Electron Devices, Vol.41, pp. 1876-1879, 1994. [2.12]Kwon-Young Choi and Min-Koo Han, “A novel gate-overlapped LDD poly-Si thin-film transistor,” IEEE Electron Device Lett., Vol. 17, pp.566-568, 1996. [2.13]N. D. Young, G. Harkin, R. M. Bunn, D. J. McCulloch, and I. D. French,“The fabrication and characterization of EEPROM arrays on glass using a low-temperature poly-Si TFT process,” IEEE Trans. Electron Devices,Vol. 43, No. 11, pp. 1930-1936, 1996. [2.14]R. K. Watts and J. T. C. Lee, “Tenth-Micron Polysilicon Thin-film Transistors,” IEEE Electron Device Lett., Vol. 14, pp.515-517, 1993. [2.15]“Polycrystalline silicon for integrated circuits and displays”, second edition, written by Ted Kamins, pp.200-210. [2.16]H. J. Kim and J. S. Im: Appl. Phys. Lett. 68 (1996) 1513. Reference [3-1] J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider, “Conductivity behavior in polycrystalline semiconductor thin film transistors,”J. Appl. Phys.,vol. 53, no. 2,pp.1193-1202,Feb. 1982. [3-2] R. E. Proano, R. S. Misage, and D. G. Ast, “Development and electrical properties of undoped polycrystalline silicon thin-film transistor,” IEEE Trans. Electron Devices, vol. 36, no. 9, pp. 1915-1922, Sep. 1989. Reference [4.1]T.-J. King, M. G. Hack, and I.-W. Wu, “Effective density-of-states distributions for accurate modeling of polycrystalline-silicon thin-film transistors,” J. Appl. Phys.,vol. 75,no. 2,pp. 908-913,Jan. 1994. [4.2]C. A. Dimitriadis, P. A. Coxon, L. Dozsa, L. Papadimitriou, and N. Economou, “Performance of thin-film transistors on polysilicon films grown by low-pressure chemical vapor deposition at various pressures,” From IEEE Trans. Electron Devices, vol. 39, no.3, pp. 598-606, Mar. 1992. [4.3]Chih-Yang Chen, Jam-Wem Lee, Shen-De Wang, Ming-Shan Shieh, Po-Hao Lee, Wei-Cheng Chen, Hsiao-Yi Lin, Kuan-Lin Yeh, and Tan-Fu Lei, “Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors,” From IEEE Trans. Electron Devices, vol. 53, no. 12, December 2006. [4.4]Satoshi INOUE, Hiroyuki OHSHIMA and Tatsuya SHIMODA, “Analysis of Degradation Phenomenon Caused by Self-Heating in Low-Temperature-Processed Polycrystalline Silicon Thin Film Transistors,” From Jpn. J. Appl. Phys. Vol. 41 (2002) pp.6313-6319, Part 1, No. 11A, November 2002. [4.5]S. Hashimoto, Y. Uraoka, T. Fuyuki, and Y. Morita, “Analysis of thermal distribution in low- temperature polycrystalline silicon p-channel thin film transistors,” Jpn. J. Appl. Phys., 45, pp. 7-12, 2006. [4.6] S. Ogawa and N. Shiono, “Generalized diffusion-reaction model for the low-field charge-buildup instability at the Si−SiO2 interface,” Phys. Rev. B, Condens. Matter, 51, pp. 4218–4230, 1995. [4.7] A.O. Adan, H. Tsutsui, M. Horita, K. Fujimoto, K. Nakai, T. Inufushi, and R. Miyake, “Analysis and model of leakage current mechanism in polysilicon MOS thin-film transistors,” in Proc. Int. Semiconductor Device Res. Symp., Charlottesville, pp. 525-528, Dec. 1991. [4.8] G. Fortunato, A. Pecora, G. Tallarida, L. Mariucci, C. Reita, and P. Migliorato, “Hot Carrier Effects in n-Channel Poly crystalline Silicon Thin-Film Transis tors : A Correlation Between Off-Current and Transconductance Variations” IEEE Trans. ON Electron Dev., VOL 41, NO 3, Mar. 1994 [4.9] S. M. Sze, and K. K. NG, “Physics of semiconductor device,” published by John Wiley & Sons, pp. 337 (2007). [4.10] S. Hashimoto, Y. Uraoka, T. Fuyuki, and Y. Morita, “Analysis of thermal distribution in low- temperature polycrystalline silicon p-channel thin film transistors,” Jpn. J. Appl. Phys., 45, pp. 7-12, 2006. [4.11] J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider, “Conductivity behavior in polycrystalline semiconductor thin film transistors,” J. Appl. Phys., vol. 53, no. 2, pp. 1193–1202, Feb. 1982. R. E. Proano, R. S. Misage, and D. G. Ast, “Development and [4.12] R. E. Proano, R. S. Misage, and D. G. Ast, “Development and electricalproperties of undoped polycrystalline silicon thin-film transistor,” IEEE Trans. Elec. Dev., vol. 36, no. 9, pp. 1915–1922, Sep. 1989.
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