臺灣博碩士論文加值系統

在這篇論文中，為了消除製程因素影響，我們採用外界機械單軸張硬力與壓應力在金氧半場效電晶體上來研究負偏壓溫度不穩定之特性。在單軸張應力下汲極電流與電洞遷移率皆減少，且負偏壓溫度不穩定之特性變得更嚴重。在單軸壓應力下汲極電流與電洞遷移率皆增加，且負偏壓溫度不穩定之特性更輕微。藉著分離式電容量測法，可發現單軸張應力下與單軸壓應力下，在反轉層的電荷分別增加與減少。這是因為應力會導致能帶分裂與有效質量改變。根據反應與擴散模型，介面缺陷產生率正比於反轉層的電動數目。因此藉著單軸張應力，因為反轉層的載子增加導致較差的負偏壓溫度不穩定之特性。但藉著單軸壓應力因為反轉層的載子減少導致較好的負偏壓溫度不穩定之特性。

In this thesis, in order to eliminate process issue, an external mechanical uniaxial tensile and compressive stress applied on p-type metal-oxide-semiconductor field effect transistors (p-MOSFETs) is used for the study of negative bias temperature instability (NBTI) characteristics. Drain current and hole mobility decreases under uniaxial tensile strain, and the NBTI characteristics also become more serious simultaneously. And drain current and hole mobility increases under uniaxial compressive strain, and the NBTI characteristics also become less serious simultaneously. By analyzing split capacitance-voltage (C-V) characteristics, inversion charge increases and decreases due to strain induced change of band splitting and effective mass under uniaxial tensile strain and uniaxial compressive strain, respectively. According to Reaction-Diffusion model, interface trap generation rate is proportional to the number of holes in inversion layer. Therefore, the worse NBTI degradation resulted from increased inversion charge induced by uniaxial tensile strain. And the better NBTI degradation resulted from decreased inversion charge induced by uniaxial compressive strain.

Chinese Abstract
English Abstract
Figures Captions
Chapter 1- Introduction
1-1 Semiconductor Device Building Blocks………………………...1
1-2 Strain Technology……………………………………………….3
1-3 Motivation………………………………………………………..8
1-4 Organization of this Thesis……………………………………...9
Chapter 2 Foundation of Theory
2-1 MOSFET………………………………………………………..11
2-2 NBTI…………………………………………………………….12
2-2-1 Background
2-2-2 Experimental signatures of NBTI
2-2-3 The standard R–D model of NBTI
2-2-3-1 Description of the R–D model
2-2-3-2 Discussion of the R–D model
2-2-3-3. Enhancement of the R–D model
2-2-3-3-1. Model for NBTI field (or voltage) dependence
2-2-3-3-1. Role of holes and field-dependence through hole density
2-2-3-3-2. Activation energy of the diffusion process
2.3 Charge Pumping………………………………………………..24
2.3.1 Basic Theory
2-3-2-1 Fixed Amplitude Sweep
2-3-2-2 Fixed Base Sweep and Fixed Peak Sweep
2-4 Mobility Measurement by Split CV…………………………..28
Chapter 3 Apparatus and Parameters
3-1 Steps of Experiments…………………………………………..30
3-1-1 Preparation before Experiments
3-1-2 Polish the sample
3-1-3 The setting of the IV measurement
3-1-4 Mobility Measurement by Split CV
3-1-5 Charge Pumping Measurement
3-2 Parameter………………………………………………………34
3-3 Apparatus of experiment………………………………………35
3-3-1 Polishing machine
3-3-2 Measurement machine
Chapter 4 Results and Discussion
4-1 The influence of electrical analysis by strained effect………..37
4-2 The influence of reliable analysis by strained effect at invariable temperature………………………………………..38
4-3 The influence of reliable analysis by strained effect at variable temperature……………………………………………………40
4-4 The influence of CV by strained effect………………………..43
4-5 The influence of charge pumping current by strained effect..44
Chapter 5 Conclusion………………………….……………..46
Reference……………………………………………….……..47
Figures………………….……………………………………..60

Chapter 1
[1-1] S. Takagi, T. Mizuno, T.Tezuka, N. Sugiyama, T. Numata, K.Usuda, Y. Moriyama,S. Nakaharai, J. Koga, A. Tanabe, N. Hirashita, and T. Maeda, “Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator(strained-SOI) MOSFETs”, in IEDM Tech. Dig., pp.57-60, December 2003.
[1-2] S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R, Chau, G. Glass, T, Hoffman,J. Klaus, Z. Ma, B. Mcintyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar,S. Tyagi, T. Ghani, K. Mistry, M. Bohr, and Y. El-Mansy, “A logic nanotechnologyfeaturing strained-silicon”, IEEE Electron Device Lett., vol. 25, pp.191-193, April 2004.
[1-3] W. Zhao, J.He, R. E. Belford, L. Wernersson, and A. Seabaugh, “Partially depleted SOI MOSFETs under uniaxial tensile strain”, IEEE Trans. Electron Devices, vol. 51, pp.317-323, March 2004.
[1-4] J. L. Hoyt, H. M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E. A. Fitzgerald,31 and D. A. Antoniadis, “Straind silicon MOSFET technology”, in IEDM Tech. Dig., pp.23-26,December 2002.
[1-5] A. Shimizu, K. Hachimine, N. Ohki, H. Ohta, M. Koguchi, Y. Nonaka, H. Sato, and F. Ootsuka, “Local mechanical-stress control (LMC): A new technique for CMOS-performance enhancement”, IEDM Tech. Dig., pp. 433-436, December 2001.
[1-6] G. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, “NMOS Drive current reduction caused by transistor layout and trench isolation induced stress”, IEDM Tech. Dig., pp.827-830, December 1999.
[1-7] T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K.Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M.Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors”, IEDM Tech. Dig., pp.978-980,December 2003.
[1-8] A. Steegen, M. Stucchi, A. Lauwers, and K. Maex, “Silicide induced pattern density and orientation dependent transconductance in MOS transistors”, IEDM Tech. Dig., pp.497-500, December 1999.
[1-9] S. Maikap, M. H. Liao, F. Yuan, M. H. Lee, C. Huang, S. T. Chang, and C. W. Liu, ”Package-strain-enhanced device and circuit performance”, IEDM Tech. Dig., pp.233-236, December 2004.
[1-10] C. Hu, “Device challenges and opportunities”, in Symp. VLSI Tech. Dig., pp.4-5,2004
[1-11] S. Ito, H. Namba, K. Yamaguchi, T. Hirata, K. Ando, S. Koyama, S. Kuroki,N.Ikezawa, T. Suzuki, T. Saitoh, and T. Horiuchi, “Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design”, IEDM Tech. Dig., pp.247-250, December 2000.
[1-12] C. Zhi-Yuan, M. T. Currie, C. W. Leitz, G. Taraschi, E. A. Fitzgerald, J. L. Hoyt,and D. A. Antoniadis, “Electron mobility nhancement in strained-Si n-MOSFET fabricated on SiGe-on-insulator (SGOI) substrates”, IEEE Electron Device Lett., vol.22, pp.321-323, July 2001.
[1-13] S. E. Thompson, G. Sun, K. Wu, J. Kim, and T. Nishida, “Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs”, IEDM Tech. Dig., pp.221-224, December 2004.
[1-14] C. Y. Lu, H. C. Lin, and T. Y. Huang, “Impacts of Uniaxial Compressive Strain on Dynamic Negative Bias Temperature Instability of p-Channel MOSFETs,” Electrochemical and Solid-State Lett., 9 (4) G138-G140, 2006.
[1-15] H. R. Rhee, H. Lee, T. Ueno, D. S. Shin, S. H. Lee, Y. Kim, A. Samoilov, P. O. Hansson, M. Kim, H. S. Kim, and N. I. Lee, “Negative Bias Temperature Instability of Carrier-Transport Enhanced pMOSFET with Performance Boosters,” in IEDM Tech. Dig., 2005, pp. 692-695.
[1-16] A. Shickova, B. Kaczer, P. Verheyen, G. Eneman, E. San Andres, M. Jurczak, P. Absil, H. Maes, and G. Groeseneken, “Negligible Effect of Process-Induced Strain on Intrinsic NBTI Behavior,” IEEE Electron Device Lett., vol. 28, no. 3, pp. 242-244, March 2007.
Chapter 2
[2-1] Shin-ichi et al., “Sub-band structure engineering for advanced CMOS channels”, in Solid-State Electronics, pp.284-69, 2005.
[2-2] Takagi S, Koga J, Toriumi A. Tech Dig IEDM 1997:219.
[2-3] Takagi S, Hoyt JL, Welser JJ, Gibbons JF. J Appl Phys 1996;80:1567.
[2-4] Nakatsuji H, Kamakura Y, Taniguchi K. IEDM Tech Dig 2002:727.
[2-5] Fischetti MV, Ren Z, Solomon PM, Yang M, Rim K. J Appl Phys 2003;94:1079.
[2-6] E. H. Nicollian, A. Goetzberger, and C. N. Berglund, “Avalanche injection currents and charging phenomena in thermal SiOX:” Appl. Pkys. Lett., vol. 15, no. 6, p. 174, 1969.
[2-7] H. K. J. Ihantola and J. L. Moll, “Design Theory of a surface field-effect transistor”, Solid State Electron., 7, 426, 1964.
[2-8] C. T. Sah, “Characteristics of metal-oxide-semiconductor transistor”, IEEE Tran. Electron Device, ED-11, 324, 1964.
[2-9] S. R. Hotstein and F. P. Heiman, “The silicon insulated-gate field-effect transistor”, Proc. IEEE, 51, 1190, 1963.
[2-10] J. T. Wallmark and H. Johnson. Field Effect Transistors, Physics, Technology, and Applications, Prentice-Hall. Englewood Clffs, N. J., 1966.
[2-11] P. Richman, MOSFET`s and Integrated Circuits, Wiley, New York, 1973.
[2-12] J. R. Brews, “Physics of the MOS transistor”, in D. Kahng, Ed., Applied Solid State, Suppl. 2A. Academic, New York, 1981.
[2-13] L. L. Chang and H. N. Yu, “The germanium insulate-gate field-effect transistor(FET)”, Prob. IEEE, 53, 316,1965.
[2-14] C. W. Wilmsen and S. Szpak, “MOS processing for Ⅲ-Ⅴ compound semiconductors : overview and bibliography”, Thin Solid Film, 46, 17, 1977.
[2-15] “Looking ahead to the Year 2000. Technology”, Electronics, 53.(9)530, 1980.
[2-16] G. Moore, “VLSI : some fundamental challenges”, IEEE Spectrum, 16(4)30, 1980.
[2-17] Deal BE, Sklar M, Grove AS, Snow EH. Characteristics of the surface-state charge (Qss) of thermally oxidized silicon. J Electrochem Soc 1967;114:266.
[2-18] Strain RJ, Goetzberger A, Lopez AD. On the formation of surface states during stress aging of thermal Si–SiO2 interfaces. J Electrochem Soc 1973;120:90.
[2-19] Frohman-Bentchkowsky D. A fully decoded 2048-bit electrically programmable FAMOS readonly memory. IEEE J Solid State Circuits 1971;6(5):301–6.
[2-20] Nakagiri M. Jpn J Appl Phys 1974;13:1619.
[2-21] Jeppson KO, Svensson CM. Negative bias stress of MOS devices at high electric fields and degradation of MOS devices. J Appl Phys 1977;48:2004–14.
[2-22] Hu C, editor. Nonvolatile semiconductor memories: technology, design, and applications. Piscataway, NJ: IEEE Press; 1991.
[2-23] Chaparala P, Shibley J, Lim P. Threshold voltage drift in p-MOSFETs due to NBTI and HCI. In: Proc Int Reliability Workshop, 2000. p. 95–7.
[2-24] La Rosa G, et al. NBTI––channel hot carrier effects in p-MOSFETs in advanced CMOS technologies. In: Proc Int Reliability Phys Symp, 1997. p. 282–6.
[2-25] Uwasawa K, Yamamoto T, Mogami T. A new degradation mode of scaled p+ polysilicon gate p-MOSFETs induced by bias temperature instability. In: Proc Int Electron Device Meet, 1995. p. 871–4.
[2-26] Kimizuka N, Yamamoto T, Mogami T, Yamaguchi K, Imai K, Horiuchi T. The impact of bias temperature instability for direct tunneling ultra-thin gate oxide on MOSFET scaling. In: Proc VLSI Tech Symp, 1999. p. 73–4.
[2-27] Yamamoto T, Uwasawa K, Mogami T. Bias temperature instability in scaled p+ polysilicon gate p-MOSFETs. IEEE Trans Electron Devices 1999;46(5):921–6.
[2-28] Makabe M, Kubota T, Kitano T. Bias temperature degradation of p-MOSFETs: mechanism and suppression. In: Proc Int Reliability Phys Symp, 2000. p. 205–9.
[2-29] Ogawa S, Shiono N. Generalized diffusion–reaction model for the low-field charge build up instability at the Si–SiO2 interface. Phys Rev B 1995;51(7):4218–30.
[2-30] Alam M, Weir B, Silverman P. The prospect of using thin oxides for silicon nano transistor. In: Proc Int Workshop on Gate Insulator, 2001. p. 10–3.
[2-31] Mahapatra S, Alam MA. A predictive reliability model for PMOS bias temperature degradation. In: Proc Int Electron Device Meet, 2002. p. 505–9.
[2-32] Mahapatra S, Bharat Kumar P, Alam MA. A new observation of enhanced bias temperature instability in thin gate oxide p-MOSFETs. In: Proc Int Electron Device Meet, 2003. p. 337–41.
[2-33] Mitani Y, Nagamine M, Satake H, Toriumi A. NBTI mechanism in ultra-thin gate dielectric-nitrogen-originated mechanism in SiON. In: Proc Int Electron Device Meet, 2002. p. 509–12.
[2-34] Schroder DK, Babcock JA. Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing. J Appl Phys 2003;94:1–18.
[2-35] Nishida Y, et al. SoC CMOS technology for NBTI/HCI immune I/O and analog circuits implementing surface and buried channel structures. In: Proc Int Electron Device Meet, 2001. p. 869–72.
[2-36] Alam M. A critical examination of the mechanics of dynamic NBTI for p-MOSFETs. In: Proc Int Electron Device Meet, 2003. p. 346–9.
[2-37] Chen G, et al. Dynamic NBTI of PMOS transistors and its impact on device lifetime. In: Proc Int Reliability Phys Symp, 2003. p. 196–202.
[2-38] Huard V, Monsieur F, Ribes G, Bruyere S. Evidence for hydrogen-related defects during NBTI stress in p-MOSFETs. In: Proc Int Reliability Phys Symp, 2003. p. 178–82.
[2-39] Tsujikawa S, et al. Negative bias temperature instability of pMOSFETs with ultra-thin SiON gate dielectrics. In: Proc Int Reliability Phys Symp, 2003. p. 183–8.
[2-40] McPherson JW, Khamankar RB, Shanware A. Complementary model for intrinsic time dependent dielectric breakdown in SiO2 dielectrics. J Appl Phys 2000;88(9): 5351–9.
[2-41] G. La Rosa, IRPS Tutorial, 2003.
[2-42] Blat CE, Nicollian EH, Poindexter EH. Mechanism of negative bias temperature instability. J Appl Phys 1991; 69:1712.
[2-43] Liu C-H et al. Mechanism of threshold voltage shift (DVth) caused by negative bias temperature instability (NBTI) in deep submicron pMOSFETs. Jpn J Appl Phys 2002;41: 2423–5.
[2-44] Alam M, Bude J, Ghetti A. Field acceleration for oxide breakdown––can an accurate anode hole injection model resolve the E vs. 1=E controversy? In: Proc Int Reliability Phys Symp, 2000. p. 21–6.
[2-45] Soon J et al. Study of negative bias temperature-instability-induced defects using first-principle approach. Appl Phys Lett 2003;83:3063–5.
[2-46] Tan SS et al. Nitrogen-enhanced negative bias temperature instability: An insight by experiment and first-principle calculations. Appl Phys Lett 2003;82:1881–3.
[2-47] Ushio J, Maruizumi T, Abdelghafar KK. Interface structures generated by negative-bias temperature instability in Si/SiO2 and Si/SiOxNy interfaces. Appl Phys Lett 2002;81: 1818–20.
[2-48] Reed ML, Plummer JD. Chemistry of Si–SiO2 interface trap annealing. J Appl Phys 1988;63:5776–93.
[2-49] J.S. Brugler, and P.G.A. Jespers, “Charge Pumping in MOS Devices”, IEEE Trans. on Electron Devices, vol. 16, pp. 297-302, March 1969.
[2-50] P. Heremans, J. Witters, G. Groeseneken,and H. E. Maes, “Analysis of the charge pumping technique and its application for the evaluation of the MOSFET Degradation”, IEEE Tran. Electron Devices, Vol. 36, No. 7, pp. 1318-1335, 1989.
[2-51] G. Groeseneken, H. E. Maes, N. Beltran, and R. F. De Kecrsmaecker, “A reliable approach to charge-pumping measurements in MOS transistors”, IEEE Trans. Electron Devices, Vol. ED-31, pp. 42-53, 1984.
[2-52]S. S. Chung, S.-J. Chen, C.-K. Yang, S.-M. Cheng, S.-H. Lin, Y.-C. Sheng, H.-S. Lin, K.-T. Hung, D.-Y. Wu, T.-R. Yew, S.-C. Chien, F.-T. Liou, and F, Wen, “A Novel and Direct Determination of the Interface Traps in Sub-100nm CMOS Devices with Direct Tunneling Regime (12-16A) Gate oxide,” VLSI Tech. Symposium, 2002.
[2-53]Pascal Masson, Jean-Luc Autran, and Jean Brini, “On the Tunneling Component of Charge Pumping Current in Ultrathin Gate Oxide MOSFET’s,” Electron Device Lett., pp. 92-94, 1999
[2-54]E. P. Gusev and C. P. D’Emic, ” Charge detrapping in HfO2 high-k gate dielectric stacks,” Appl. Phys. Lett., Vol. 83, pp5223, 2003.
Chapter 4
[4-1]T. Guillaume, and M. Mouis, “Calculations of hole mass [110]-uniaxially strained silicon for the stress-engineering of p-MOS transistors,” Solid-State Electronics, 50, pp. 701-708, 2006.
[4-2]Dieter K. Schroder, “Negative bias temperature instability: What do we understand,” Microelectronics Reliability, 47, pp. 841-852, 2007.
[4-3]S. Ogawa, and N. Shiono, “Generalized diffusion-reaction model for the low-field charge-buildup instability at the Si-SiO2 interface,” Phys. Rev. B, vol. 51, no. 7, pp. 4218-4230, February 1995.
[4-4]H. R. Rhee, H. Lee, T. Ueno, D. S. Shin, S. H. Lee, Y. Kim, A. Samoilov, P. O. Hansson, M. Kim, H. S. Kim, and N. I. Lee, “Negative Bias Temperature Instability of Carrier-Transport Enhanced pMOSFET with Performance Boosters,” in IEDM Tech. Dig., 2005, pp. 692-695.
[4-5]A. Shickova, B. Kaczer, P. Verheyen, G. Eneman, E. San Andres, M. Jurczak, P. Absil, H. Maes, and G. Groeseneken, “Negligible Effect of Process-Induced Strain on Intrinsic NBTI Behavior,” IEEE Electron Device Lett., vol. 28, no. 3, pp. 242-244, March 2007.
[4-6]M. A. Alam, and S. Mahapatra, “A comprehensive model of PMOS NBTI degradation,” Microelectronics Reliability, 45, pp. 71-81, 2005.
[4-7]Md. Itrat Bin Shams, Md. Kawsar Alam, and Quazi D. M. Khosru, “Effects of Uniaxial Strain on the Gate Capacitance of Double Gate MOSFETs,” in EDSSC, 2008, pp. 1-4.
[4-8]Md. Manzur Rahman, “A Theoretical Study of Electrostatic Properties of <110> Uniaxially Strained Silicon n-Channel MOSFET,” in ICSICT, 2008, pp. 142-145.