臺灣博碩士論文加值系統

摘 要

現今的半導體製程技術已進入奈米尺度，隨著製程不斷的微縮，使單位面積的晶片能夠擁有更多的電晶體數量，進而提昇其工作頻率及性能，但是微影技術有其技術瓶頸。而且功率電晶體在應用上要求能夠兼顧高驅動電流和高耐壓性，而縮短元件的飄移區，將會降低功率電晶體的耐壓性，不符合目的。所以除了微縮方法，我們必須尋找其他能夠提升電晶體效能的方法，應變矽就是其中一種方法。在此論文裡，研究者深入探討當N-type功率電晶體的通道受到應變時，對其電性特性與可靠度之影響。

為了讓通道產生應變，我們選擇利用施予外界機械應力(Bending)來彎曲矽基板，此時通道將受到單軸張應力而產生應變。利用此方法，我們成功提高功率電晶體的汲極電流12.1%，提升載子遷移率4.1%。造成電子遷移率提升的主要因素是二重與四重簡併間能帶的明顯分裂。

另外，在可靠度分析方面，藉由 2000 秒的 D.C Stress，我們可以瞭解熱載子效應對應變矽的影響。功率元件尺寸越長（包含Lg和DL），可靠度越好。經過Bending處理之元件，可靠度略有改善，並且其影響和 Drift Length 直接相關。對於通道Lg=0.8(m的元件，給予曲率R=40mm的Bending，比起平面元件可得到更好的可靠度。

Abstract

The tendency to manufacture of semiconductor is to minimize the size of device. With the size was minimized, the number of transistor on the chip was maximized at the same time .However, when the drift region of Power-MOSFET is shorter will result in the Breakdown Voltage is lower, so this do not conform our purpose for application, and therefore we should look for some alternative method to enhance efficiency.
One of these method of efficiency promotion is adopting channel strain. We adopt bending silicon substrate to obtain strain. By using this method, we successfully enhance drain current and mobility 12.1% and 4.1% individually.
Furthermore, regarding the reliability study, we realize the hot-carrier effect influence under strain silicon. The longer the size(Lg & DL) of Power- MOSFET , the reliability is better. When device were bent under Bending R=40mm and Lg=0.8(m conditions, we can obtain the better reliability of device than flat chip.

目 錄

中文摘要 Ⅰ
英文摘要 Ⅱ
目 錄 Ⅲ
圖 次 Ⅴ
表 次 Ⅷ
符號一覽表 Ⅸ

第一章 緒論
1-1.功率電晶體的應用 1
1-2.研究動機 3
1-3.文獻回顧 4
1-4.本文結構 5

第二章 理論基礎
2-1. MOSFET構造和原理 6
2-2. 功率電晶體（Power-MOSFET） 12
2-3. 外加機械應力於功率電晶體 22

第三章 實驗儀器與實驗步驟介紹
3-1.實驗儀器 26
3-1-1. 研磨機 26
3-1-2. 量測機台 27
3-2.實驗步驟 29
3-2-1. 實驗前準備 29
3-2-2. Sample研磨 29
3-2-3. 量測設定 30
3-2-4. Sample規格及量測點 33
3-3.參數萃取 34
第四章 結果與討論
4-1.功率電晶體的基本電性 37
4-2.Breakdown Voltage與Ron 40
4-3.室溫時Bending效果的電性分析 47
4-4.高溫時Bending效果的電性分析 54
4-5.可靠度研究 58

第五章 結論與未來展望
5-1.結論 63
5-2.未來展望 64

參考文獻 65

參 考 文 獻

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