臺灣博碩士論文加值系統

隨著消費性電子產品的應用越來越廣泛，同一個晶片上可以執行的功能也越來越多，但相對於整體供應電壓上的考量，不同區塊電路所需要的供應電壓也會不一樣，因此需要不同的供應電壓，另外在功率消耗的考量上，電路工作在低電壓與低電流時能降低功率的消耗。隨著能源危機的影響，許多產品都開始注意所謂的綠色能源，綠色能源主要優點在於能夠更省電，但整體效率不會變差為主。此外，在製程技術不斷地演進的同時，由於可靠度的考量，其工作電壓也必須隨著製程的進步而降低。因此本論文應用在一個3D 繪圖IC晶片的電源管理上，利用線性穩壓器將供應電壓3.3V降至1.2V, 1.1V, 1.0V, 0.9V, 0.8V的輸出電壓，並提供穩定的電壓給核心電路及I/O電路。隨著電源管理直接影響到電路的功率消耗越來越被注重，本論文也著重在利用電壓準位調升電路嵌入進一般常用的數位邏輯閘中，讓在使用邏輯閘的同時也可以利用電壓準位調升電路的特性降定整體的功率消耗，因此電源IC在未來的產品應用上變的更重要。

As the application of the consuming electronic products being used extensively, more and more functions can be worked on the same chip. Different function blocks may need different supply voltage. Considering of power consumption, circuit operated at low voltage and low current can achieve power reduction. Due to the energy crisis nowadays, plenty of products begin to focus on the green power. The main advantage of green power is saving power, which will not affect the efficiency. In addition, while the CMOS technology process evolves all the time, the stability of the operation voltage needs to be reduced by the advancement. Thus, the power management in a 3D graphic chip application is going to be introduced in this thesis. Utilizing the linear regulator to reduce the DC to 1.2, 1.1, 1.0, 0.9 and 0.8 V from 3.3V, and support a stable voltage for core circuits and I/O circuits. With the emphasis on the circuit efficiency is affected by power management, the level shifter to embed normal useful digital logic is also investigated. When using in the logic gates, it can reduce power consumption simultaneously. Therefore, it is important to adopt power IC in the future.

CHAPTER 1 Introduction .................................................................................................. 1
1.1 Introduction........................................................................................................... 1
1.2 Motivation............................................................................................................. 1
1.3 Research Goals and Contribution ......................................................................... 2
1.4 Thesis Organization .............................................................................................. 3
CHAPTER 2 Introduction of Voltage regulator................................................................. 4
2.1 Introduction........................................................................................................... 4
2.2 Basic Regulator..................................................................................................... 4
2.2.1 Basic low dropout linear regulator architecture......................................... 5
2.2.2 Basic Switch regulator architecture ........................................................... 7
2.3 Specifications and Definitions of LDO................................................................. 9
2.3.1 Dropout Voltage ......................................................................................... 9
2.3.2 Quiescent Current .................................................................................... 11
2.3.3 Current Efficiency.................................................................................... 12
2.3.4 Efficiency................................................................................................. 13
2.3.5 Load Regulation....................................................................................... 13
2.3.6 Line Regulation........................................................................................ 14
2.3.7 Power Supply Rejection........................................................................... 15
2.3.8 Pass Devices Design ................................................................................ 15
2.3.9 ESR of Output Capacitor ......................................................................... 18
CHAPTER 3 The LDO Architecture................................................................................ 20
3.1 Architecture......................................................................................................... 20
3.1.1 The LDO circuit Architecture Implementation........................................ 22
3.2 Bandgap Reference ............................................................................................. 23
3.2.1 Conventional Bandgap Voltage Reference .............................................. 23
3.2.2 The Bandgap Reference Analysis ............................................................ 24
3.3.3 Circuit Implementation ............................................................................ 28
3.3 Error Amplifier.................................................................................................... 31
3.4 Summary ............................................................................................................. 32
CHAPTER 4 LDO Simulations........................................................................................ 33
CHAPTER 5 Dynamic Level Converter Logic ................................................................ 41
5.1 Multiple Voltage Techniques............................................................................... 41
5.2Conventional Level Shifter Circuit...................................................................... 44
5.3 Dynamic Logic.................................................................................................... 46
5.4 Dynamic Logic Combined Level Shifter............................................................ 47
5.5 Other Level Shifter Structure.............................................................................. 48
5.6 Improvement Level Converter............................................................................ 54
5.7 Combination of Level Converter ........................................................................ 55
CHAPTER 6 Simulations for Level Converter ................................................................ 57
CHAPTER 7 Layout of All Circuits................................................................................. 66
7.1 Layout ................................................................................................................. 66
CHAPTER 8 Conclusion and Future Works .................................................................... 71
8.1 Conclusion .......................................................................................................... 71
8.2 Futures Works..................................................................................................... 71
References........................................................................................................................ 72

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[43] 張裕睿，具有PVT容忍能力之CMOS電壓準位調升電路，國立中正大學電機工
程研究所碩士論文，民國九十四年。