隨著製程的進步，系統的可測試性變得越來越重要。多掃描樹的測試架構可以有效的增加資料的壓縮率與降低測試時間，進而節省測試成本。在過去有關掃描樹合成演算法的相關研究中，大多僅考量掃描樹的壓縮率與測試時間，對於掃描樹所增加的硬體設計負擔則著墨較少。其合成出來的掃描樹往往擁有繞線過長、掃描輸出(scan out)過多…等缺點，使得掃描樹難以應用在實際設計中。在這篇研究中，我們同時考量繞線長度與SO的數量及位置的限制，提出一個新的多掃描樹合成演算有效地降低了掃描樹所需要的繞線長度，並且保持掃描樹既有的高資料壓縮率與低測試時間等優點。

A synthesis methodology for multiple scan trees that considers output pin limitation, scan chain routing length, test application time and test data compression rate simultaneously is proposed in this thesis. Multiple scan trees, also known as a scan forest, greatly reduce test data volume and test application time in SOC testing. However, previous research on scan tree synthesis rarely considered issues such as routing length and output port limitation, and hence created scan trees with a large number of scan output ports and excessively long routing paths. The proposed algorithm provides a mechanism that effectively reduces test time and test data volume, and routing length under output port constraint. As a result, no output compressors are required, which significantly reduce the hardware overhead.

Chapter 1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Chapter 2 PRELIMINARIES 5
2.1 Test Vector Compatibility in Single Scan Chain . . . . . . . . . . . . . . . . 5
2.2 Test Vector Compatibility in Scan Tree . . . . . . . . . . . . . . . . . . . . . 6
2.3 Scan Tree with Inverse Compatibility . . . . . . . . . . . . . . . . . . . . . 6
Chapter 3 PROBLEM DEFINITION 9
Chapter 4 SCAN OUT REDUCTION (SOR) ALGORITHM FOR MULTIPLE
SCAN TREE SYNTHESIS 11
4.1 Phase I: Initial Regions Partition . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Phase II: Output-Driven Scan Direction Selection . . . . . . . . . . . . . . . 11
4.3 Phase III: Size-Driven Cells Partition . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Phase IV: Compatibility Group Construction . . . . . . . . . . . . . . . . . . 14
4.5 Phase V: Level-to-Level Physical Connection . . . . . . . . . . . . . . . . . 17
4.5.1 Reduce Weights in the Distance Matrix . . . . . . . . . . . . . . . . 17
4.5.2 Find the Minimum Matching . . . . . . . . . . . . . . . . . . . . . . 18
4.5.3 Modify the Distance Matrix . . . . . . . . . . . . . . . . . . . . . . 18
4.6 Phase VI: Scattered Cells Connection . . . . . . . . . . . . . . . . . . . . . 18
4.6.1 Connecting Cells to Existing Scan Trees . . . . . . . . . . . . . . . . 20
4.6.2 Constructing Multiple Scan Chains . . . . . . . . . . . . . . . . . . 21
4.6.2.1 Step 1: Assign cell weights . . . . . . . . . . . . . . . . . 21
4.6.2.2 Step 2: Select cells in each chain . . . . . . . . . . . . . . 22
4.6.2.3 Step 3: Connect cells into scan chains . . . . . . . . . . . 22
4.7 Scan Out Reduction Algorithm Flow . . . . . . . . . . . . . . . . . . . . . . 22
Chapter 5 EXPERIMENTAL RESULTS 25
Chapter 6 CONCLUSION 28
Bibliography 29

[1] K. S.-M. Li and J.-Y. Huang, “Interconnect-driven layout-aware multiple scan tree synthesis for test time, data compression and routing optimization,” in Proc. Asia Test Symposium, pp. 63–68, Nov. 2008.
[2] K. Miyase and S. Kajihara, “Optimal scan tree construction with test vector modification for test compression,” in Proc. Asia Test Symposium, pp. 136–141, Nov. 2003.
[3] J. D. Xiang, S. Gu, J.-G. Sun, and Y.-L. Wu, “A cost-effective scan architecture for scan testing with nonscan test power and test application cost,” in Proc. Design Automation Conference, pp. 744–747, June 2003.
[4] K. Miyase, S. Kajihara, and S. M. Reddy, “Multiple scan tree design with test vector modification,” in Proc. Asia Test Symposium, pp. 76–81, Nov. 2004.
[5] e. a. Y. Bonhomme, “An efficient scan tree design for test time reduction,” in Proc. European Test Symposium, pp. 174–179, May 2004.
[6] S. N. M. H. H. Yotsuyanagi, T. Kuchii and K. Kinoshita, “Reducing scan shifts using configurations of compatible and folding scan trees,” J. Electronic Testing, vol. 21, pp. 613–620, Dec. 2005.
[7] H. F. P. Girard, T. Yoneda and Y. Bonhomme, “Test application time reduction with a dynamically reconfigurable scan tree architecture,” in Proc. 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, pp. 19–26, Dec. 2005.
[8] B. B. S. Banerjee, D.R. Chowdhury, “An efficient scan tree design for compact test pattern set,” IEEE Trans. Comput.-Aided Design, vol. 26, pp. 1331–1339, July 2007.
[9] J. S. D. Xiang, K. Li and H. Fujiwara, “Reconfigured scan forest for test application cost, test data volume, and test power reduction,” IEEE Trans. Compuers, vol. 56, pp. 557–562, April 2007.
[10] S.-J. Wang, X.-L. Li, and K. S.-M. Li, “Layout-aware multi-layer multi-level scan tree synthesis,” in Proc. Asia Test Symposium, pp. 129–132, Oct. 2007.
[11] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, “Efficient scan chain design for power minimization during scan testing under routing constraint,”in Proc. Int. Test Conf., pp. 488–493, Sept. 2003.
[12] VLSI Test Principles and Architectures. Morgan Kaufmann Publishers, 2006.
[13] S. K. S.M. Reddy, K. Miyase and I. Pomeranz, “On test data volume reduction for multiple scan chain designs,” in Proc. VLSI Test Symposium, pp. 103–108, April 2002.
[14] M. N. A. Jas, J. Ghosh-Dastidar and N. Touba, “An efficient test vector compression scheme using selective huffman coding,” IEEE Trans. Comput.-Aided Design, vol. 22, pp. 797–806, June 2003.
[15] A. Jas and N. Touba, “Test vector compression via cyclical scan chains and its application to testing core-based designs,” in Proc. Int. Test Conf., pp. 458–464, Oct. 1998.
[16] A. Chandra and K. Chakrabarty, “System-on-a-chip test-data compression and decompression architectures based on golomb codes,” IEEE Trans. Comput.-Aided Design, vol. 20, pp. 355–368, March 2001.
[17] A. Chandra and K. Chakrabarty, “Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (fdr) codes,” IEEE Trans. Computers, vol. 52, pp. 1076–1088, Aug. 2003.
[18] B. K‥onemann, “LFSR-coded test patterns for scan design,” in Proc. European Test Cof., pp. 237–242, 1991.
[19] I. Bayraktaroglu and A. Orailoglu, “Test volume and application time reduction through scan chain concealment,” in Proc. Design Automation Conf., pp. 151–155, 2001.
[20] J.-J. C. K.-J. Lee and C.-H. Huang, “Broadcasting test patterns to multiple circuits,”IEEE Trans. Comput.-Aided Design, vol. 18, pp. 1793–1802, Dec. 1999.
[21] I. Hamzaoglu and J. Patel, “Reducing test application time for full scan embedded cores,” in Proc. Int. Symposium on Fault-Tolerant Computing, pp. 260–267, June 1999.
[22] P.-C. Tsai and S.-J. Wang, “Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction,” IET Comput. Digit. Tech., vol. 2, pp. 434–444, Nov. 2008.
[23] K. W. L. D. Xiang and H. Fujiwara, “Design for cost effective scan testing by reconfiguring scan flip-flops,” in Proc. Asia Test Symposium, pp. 18–21, Dec. 2005.
[24] I. Hamzaoglu and J. Patel, “Test set compaction algorithms for combinational circuits,”in Proc. Int. Conf. Comput.-Aided Design, pp. 283–289, Nov. 1998.
[25] S. Kajihara and K. Miyase, “On identifying don’t care inputs of test patterns for combinational circuits,” in Proc. Int. Conf. Comput.-Aided Design, pp. 364–369, Nov. 2001.
[26] J. Munkres, “Algorithms for the assignment and transportation problems,” Journal of the Society for Industrial and Applied Mathematics, vol. 5, no. 1, pp. 32–38, 1957.
[27] H. W. Kuhn, “The hungarian method for the assignment problem,” Naval Research Logistic Quarterly, vol. 2, pp. 83–97, 1955.
[28] K. D. Boese, A. B. Kahng, and R. S. Tsay, “Scan chain optimization: Heuristic and optimal solutions,” in UCLA CS Dept., OCT. 1994.
[29] J.-S. Chang and C.-S. Lin, “Test set compaction for combinational circuits,” IEEE Trans. Comput.-Aided Design, vol. 14, pp. 1370–1378, Nov. 1995.