臺灣博碩士論文加值系統

本篇論文提出一個多分區記憶體架構之矩陣轉置電路產生器設計方法。由此方法所產生的矩陣轉置電路架構適合應用於處理矩陣大小較大的矩陣轉置運算。由於利用暫存器來儲存矩陣轉置所需的資料將佔用較大的硬體面積，因此提出的架構將採用靜態存取記憶體作為資料儲存的裝置。另外，針對單存取埠靜態存取記憶體(single-port SRAM)在使用上的限制，因此本篇論文提出了一個記憶體分區配置演算法(Two-way group expansion bank allocation algorithm)，用來在每一個周期中可以使輸入或者是輸出的矩陣資料分別存取到不同分區的記憶體。除此之外，演算法所產生的結果更可以提供自動合成負責資料位移的輸入路徑選擇器(Input router)與輸出路徑選擇器(Output router)。最後，一個專屬的資料擷取位址產生器(data fetch address generator)電路架構也在本文中提出。其產生位址的過程中利用了基底位址產生器(group-base address generator)與偏移量位址產生器(offset address generator)的硬體架構來完成，此兩個部分可由移位暫存器陣列(shift-register array)與唯讀記憶體資料表(on-chip ROM table)組成。另外，論文中所提出的設計方法可以將其實現成一個矩陣轉置電路產生器。此產生器可以產生相對應的矩陣轉置電路，並且此電路的執行頻率可在一百萬赫茲以上。實驗結果顯示，利用多分區記憶體作為儲存單元的矩陣轉置電路與利用暫存器做為儲存裝置的電路相比，可以有效減少硬體電路所需的邏輯閘。

A novel design methodology of parallel VLSI matrix transposer circuit based on a multi-bank memory architecture is presented. The proposed transposer design is especially suitable for large matrix applications where the use of registers to store the matrix data become inefficient. Due to the limited access ports of single SRAM module, this paper first proposes a two-way group expansion bank allocation algorithm such that each of the input or the output data presented in each cycle belongs to separate banks of memory. Next, the allocation results can be further utilized to automatically synthesize the input and output data-path router based on a two-level data switch architecture. Finally, a dedicated data fetch address generator circuit is also proposed, which divides the address generation into two parts. These parts include group base and offset address generation which can be simply realized by a shift-register array and a small on-chip ROM table, respectively. The proposed design methodology has been implemented as a systematic transposer generator which can generate the soft Verilog code. It can generate very fast transposer which can run at one hundred fifty mega hertz. Our experimental results from several design cases show that our multi-bank memory based transposer can consume much less gates compared with register-based transposer architecture.

Chapter 1 概論 1
1.1 研究動機 1
1.2 論文大綱 2
Chapter 2 研究背景與相關研究3
2.1 矩陣轉置器簡介3
2.2 矩陣轉置器相關研究3
Chapter 3 基於記憶體之矩陣轉置電路架構6
Chapter 4 平行矩陣轉置器之設計方法12
4.1 資料分配技術13
4.2 輸入控制電路23
4.3 輸出控制電路28
Chapter 5 實驗結果36
Chapter 6 結論與未來目標40
6.1 結論40
6.2 未來目標40
List of Figure
圖表 1-1. 3 x 3 矩陣轉置示意圖 7
圖表 3-1. 基於記憶體之序列矩陣轉置器示意圖 . 7
圖表 3-2. 位址產生器電路圖 . 8
圖表 3-3. 平行矩陣轉置之不同記憶體架構實例 . 10
圖表 4-1. 基於多分區記憶體之矩陣轉置器架構示意圖 . 13
圖表 4-2. 配置表建構實例 . 15
圖表 4-3. 記憶體分區配置演算法 . 16
圖表 4-4. 配置表建構實例 - 矩陣大小8 x 6、平行階層12 21
圖表 4-5. 輸入控制電路之電路圖 . 27
圖表 4-6. 輸出控制電路之電路圖 . 30
圖表 4-7. 8 x 6 矩陣、平行階層12 矩陣轉置器之讀取位址矩陣 33
圖表 4-8. 8 x 6 矩陣、平行階層12 矩陣轉置器之群基底與偏移量位址矩陣 33
圖表 4-9. 位址產生器電路之電路圖 . 35
圖表 5-1. 4 x 4 矩陣轉置之轉置器單元電路架構圖 37
圖表 5-2. 矩陣轉置產生器之圖形使用者介面 . 39
圖表 附錄-1. 錯誤建構實例之配置表矩陣bM - (1) . 43
圖表 附錄-2. 錯誤建構實例之配置表矩陣bM - (2) . 44
圖表 附錄-3. 正確建構實例之配置表矩陣bL 45
圖表 附錄-4. 正確建構實例之配置表矩陣bH . 46
圖表 附錄-5. 正確建構實例之配置表矩陣bM 列建置過程 47
圖表 附錄-6. 正確建構實例之配置表矩陣bV 47
圖表 附錄-7. 正確建構實例之配置表矩陣bM 行建置過程 48
圖表 附錄-8. 正確建構實例之配置表矩陣bM . 49
List of Table
表格 4-1. 8 x 6 矩陣、平行階層12 矩陣轉置器之資料輸入儲存表 22
表格 4-2. 8 x 6 矩陣、平行階層12 矩陣轉置器之輸出資料擷取表 22
表格 5-1. 不同架構之矩陣轉置器邏輯閘數量比較表 . 37
表格 5-2. 不同擷取位址產生器設計之比較表 . 39

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