|
[1]M. A. Margarit, D. Shih, P. J. Sullivan, and F. Ortega, “A 5-GHz BiCMOS RFIC front-end for IEEE 802.11a/HiperLAN wireless LAN,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1284-1287, July 2003. [2]Z. Li, R. Quintal, and K. K. O, “A dual-band CMOS front-end with two gain modes for wireless LAN applications,” IEEE J. Solid-State Circuits, vol. 39, pp. 2069-2073, Nov. 2004. [3]S. Sarkar, P. Sen, A. Raghavan, S. Chakarborty, and J. Laskar, “Development of 2.4 GHz RF transceiver front-end chipset in 0.25μm CMOS,” in Proc. 16th Int. VLSI Design Conf., Jan. 2003, pp. 42-47. [4]K. Vavelidis, I. Vassiliou, T. Georgantas, A. Yamanaka, S. Kavadias, G. Kamoulakos, C. Kapnistis, Y. Kokolakis, A. Kyranas,P. Merakos, I. Bouras, S. Bouras, S. Plevridis, and N. Haralabidis, “A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-spl mum CMOS transceiver for 802.11abg wireless LAN,” IEEE J. Solid-State Circuits, vol. 39, pp. 1180-1184, July 2004. [5]B. Come, D. Hauspie, G. Albasini, S. Brebels, W. De Raedt, W. Diels, W. Eberle, H. Mind, J. Ryckaert, J. Tubbax, and S. Donnay, “Single-package direct-conversion receiver for 802.1 1 a Wireless LAN enhanced with fast converging digital compensation techniques,” in 2004 IEEE MTT-S Int. Microwave Symp. Dig., pp. 555-558. [6]S. Khorram et al., “A fully integrated SOC for 802.11b in 0.18-spl mum CMOS,” IEEE J. Solid-State Circuits, vol. 40, pp. 2492-2501, Dec. 2005. [7]P. M. Stroet et al., “A zero-IF single-chip transceiver for up to 22 Mb/s QPSK 802.11b wireless LAN,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., 2001, pp. 204–205. [8]W. Kluge et al., “A 2.4GHz CMOS transceiver for 802.11b wireless LANs,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., 2003, pp. 360–361. [9]B. Razavi, “A 2.4-GHz CMOS receiver for IEEE 802.11 wireless LAN’s,” IEEE J. Solid-State Circuits, vol. 34, pp. 1382–1385, Oct. 1999. [10] M. Zargari, D. K. Su, C. P. Yue, S. Rabii, D. Weber, B. J. Kaczynski, S. S. Mehta, K. Singh, S. Mendis, and B. A. Wooley, “A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems,” IEEE J. Solid-State Circuits, vol. 37, pp. 1688–1694, Dec. 2002. [11] M. Zargari, D. K. Su, C. P. Yue, S. Rabii, D. Weber, B. J. Kaczynski, S. S. Mehta, K. Singh, S. Mendis and B. A. Wooley, “A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems,” IEEE J. Solid-State Circuits, vol. 37, pp. 1688-1694, Dec. 2002. [12] J. Ryynanen, K. Kivekas, J. Jussila, A. Parssinen and K. A. I. Halonen, “A dual-band RF front-end for WCDMA and GSM applications,” IEEE J. Solid-State Circuits, vol. 36, pp. 1198-1204, Aug. 2001. [13] T. H. Lee, H. Samavati and H. R. Rategh, “5-GHz CMOS wireless LANs,” IEEE Trans. Microwave Theory and Tech., vol. 50, pp. 268-280, Jan. 2002. [14] C. Chien, Digital Radio Systems on A Chip: A Systems Approach, Norwell, MA: Kluwer Academic Publishers, 2001. [15] J. Roger and C. Plett, Radio Frequency Integrated Circuits Design, Boston, MA: Artech House Inc., 2003. [16] A. A. Abidi, “Direct-conversion radio transceivers for digital communications,” IEEE J. Solid-State Circuits, vol. 30, pp. 1399–1410, Dec. 1995. [17] B. Razavi, “Design considerations for direct-conversion receivers,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 44, pp. 428-435, June 1997. [18] B. Razavi, “Challenges in portable RF transceiver design,” IEEE Circuits and Devices Magazine, pp. 12-25, Sep. 1996. [19] Q. Gu, RF System Design of Transceivers for Wireless Communications, New York, NY: Springer Science+Business Media LLC, 2005. [20] L.E. Larson, “Integrated circuit technology options for RFIC’s – present status and future directions,” IEEE J. Solid-State Circuits, pp. 387-399, March 1998. [21] R. R. Tummala, Fundamental of Microsystems Packaging, Boston, MA: McGraw-Hill Inc., 2001. [22] A. C. Imhoff, “Packaging technologies for RFIC’s: current status and future trends,” in IEEE Radio-Freq. Integr. Circuits Symp. Dig., 1999, pp. 7–10. [23] M. A. Bolanos, “Semiconductor integrated circuit packaging technology challenges - next five years,” in Int. Electron. Material Packag. Symp. Dig., Dec. 2005, pp. 6–9. [24] L. Larson and D. Jessie, “Advances in RF packaging technologies for next-generation wireless communications applications,” in Proc. Custom Integrated Circuits Conf., 2003, pp. 323–330. [25] H. Lavoie, M.-C. Paquet, J. Sylvestre, S. Ouimet, E. Duchesne, S. Barbeau, M. Gauvin, V. Oberson, “From leaded to lead free assembly and new packaging technology challenges,” in Proc. 57th Electron. Comp. Technol. Conf., 2007, pp. 1333–1339. [26] W. Chen, The technology road-map of the advanced package in Taiwan, Available: http:// www.eiak.org/electronic_info/data/Technology.pdf [27] G. Mandall, G. Mishral, W.D. van Driell, and G.Q.Zhang, “The effects of packaging on RFICs,” in Proc. Int. Electron. Packag. Technol. Conf., Aug. 2006, pp. 1-7. [28] P. C. Cherry and M. F. Iskander, “High-frequency electronic package and interconnection effects,” in IEEE Int. AP-S. Symp. Dig., June 1994, pp. 1706-1709. [29] M. P.Gaynor, System-in-Package: RF Design and Applications, Boston, MA: Artech House Inc., 2007. [30] E. J. Vardaman, K. Carpenter, and L. Matthew, System-in-Package: The New Wave in 3D packaging, Austin, TX: TechSearch International Inc., 2005. [31] J.H. Lau and S.W.R Lee, Chip Scale Packaging: Design, Materials, Process, Reliability, and Applications, New York, NY: McGraw-Hill Inc., 1999. [32] D. Jessie and L. Larson, “Design techniques for improved microwave performance of small outline packages,” in IEEE Radio-Freq. Integr. Circuits Symp. Dig., 2002, pp. 381–384. [33] T.S. Horng, S.M. Wu, C.T. Chiu, and C.P. Hung, “Electrical performance improvements on RFICs using bump chip carrier packages as compared to standard thin shrink small outline packages,” IEEE Trans. Adv. Packag., vol. 24, pp. 548-554, Nov. 2001. [34] N. Chen, K. Chiang, T.D. Her, Y.-L. Lai, and C. Chen, “Electrical characterization of quad flat non-lead package for RFIC applications,” in Int. Semiconductor Device Research Symposium Dig., 2001, pp. 266-269. [35] T.S. Horng, S.M. Wu, H.H. Huang, C.T. Chiu, and C.P. Hung, “Modeling of lead-frame plastic CSPs for accurate prediction of their low-pass filter effects on RFICs,” IEEE Trans. Microwave Theory and Tech., vol. 49, pp. 1538-1545, Sep. 2001. [36] P. Sivonen and A. Parssinen, “Analysis and optimization of packaged inductively degenerated common-source low-noise amplifiers with ESD protection,” IEEE Trans. Microwave Theory and Tech., vol. 53, pp. 1304-1313, Apr. 2005. [37] P. Sivonen, S. Kangasmaa, and A. Parssinen, “Analysis of packaging effects and optimization in inductively degenerated common-emitter low-noise amplifiers,” IEEE Trans. Microwave Theory and Tech., vol. 51, pp. 1220-1226, Apr. 2003. [38] T.S. Horng, S.M. Wu, C.T. Chiu, and C.P. Hung, “Electrical performance improvements on RFICs using bump chip carrier packages as compared to standard thin shrink small outline packages,” IEEE Trans. Adv. Packag., vol. 24, pp. 548-554, Nov. 2001. [39] F.Y. Han, J.M. Wu, T.S. Horng, and C.C. Tu, “A rigorous study of package and PCB effects on W-CDMA upconverter RFICs,” IEEE Trans. Microwave Theory and Tech., vol. 54, pp. 3793-3804, Oct. 2006. [40] J.M. Wu, F.Y. Han, T.S. Horng, and J. Lin, “Direct-conversion quadrature modulator MMIC design with a new 90 degrees phase shifter including package and PCB effects for W-CDMA applications,” IEEE Trans. Microwave Theory and Tech., vol. 54, pp. 2691-2698, Jun. 2006. [41] R. Senthinathan and J.L. Prince, “Simultaneous switching ground noise calculation for packaged CMOS devices,” IEEE J. Solid-State Circuits, vol. 26, pp. 1724-1726, Nov. 1991. [42] A.R. Djordjevic and T.K. Sarkar, “An investigation of delta-I noise on integrated circuits,” IEEE Trans. Electromag. Compat., vol. 35, pp. 134-147, May 1993. [43] S.V. den Berghe, F. Olyslager, D. de Zutter, J.D. Moerloose, and W. Temmerman, “Study of the ground bounce caused by power plane resonances,” IEEE Trans. Electromag. Compat., vol. 40, pp. 111-119, May 1998. [44] Y. Eo, W. R. Eisenstadt, W. Jin, J. Choi, and J. Shim, “A compact multilayer IC package model for efficient simulation, analysis, and design of high-performance VLSI circuits,” IEEE Trans. Adv. Packag., vol. 26, pp. 392-401, Nov. 2003. [45] E. McGibney and J. Barrett, “An overview of electrical characterization techniques and theory for IC packages and interconnects,” IEEE Trans. Adv. Packag., vol. 29, pp. 131-139, Feb. 2006. [46] F. Ndagijimana, J. Engdahl, A. Ahmadouche, and J. Chilo, “Frequency limitation on an assembled SOP8 package,” in Proc. 43th Electron. Comp. Technol. Conf., 1993, pp. 530–535. [47] T. Y. Chou and Z. J. Cendes, “Capacitance calculation of IC packages using the finite element method and planes of symmetry,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 13, pp. 1159–1166, Sept. 1994. [48] A. C. Cangellaris, J. L. Prince, and L. P. Vakanas, “Frequency-dependent inductance and resistance calculation for three-dimensional structures in high-speed interconnect systems,” IEEE Trans. Comp., Hybrids, Manufact. Technol., vol. 13, pp. 154–159, Mar. 1990. [49] R. W. Jackson, “A circuit topology for microwave modeling of plastic surface mount packages,” IEEE Trans. Microwave Theory and Tech., vol. 44, pp. 1140–1146, July 1996. [50] R. W. Jackson and S. Rakshit, “Microwave-circuit modeling of high lead-count plastic packages,” IEEE Trans. Microwave Theory and Tech., vol. 45, pp. 1926–1933, Oct. 1997. [51] Y. Chen, P. Harms, R. Mittra, andW. T. Beyene, “An FDTD-Touchstone hybrid technique for equivalent circuit modeling of SOP electronic packages,” IEEE Trans. Microwave Theory and Tech., vol. 45, pp. 1911–1918, Oct. 1997. [52] C.-N. Kuo, B. Houshmand, and T. Itoh, “Full-wave analysis of packaged microwave circuits with active and nonlinear devices: an FDTD approach,” IEEE Trans. Microwave Theory and Tech., vol. 45, pp. 819–826, May. 1997. [53] M. Righi, G. Tardioli, L. Cascio, and W. J. R. Hoefer, “Time-domain characterization of packaging effects via segmentation technique,” IEEE Trans. Microwave Theory and Tech., vol. 45, pp. 1905-1910, Oct. 1997. [54] F. Mernyei, “Measurement and field simulation based characterization of plastic packages,” in Proc. IEEE 6th Topical Elect. Performance Electron. Packag. Meeting, 1997, pp. 181–184. [55] C. Chun, A.-V. Pham, J. Laskar, and B. Hutchison, “Development of microwave package models utilizing on-wafer characterization techniques,” IEEE Trans. Microwave Theory and Tech., vol. 45, pp. 1948-1954, Oct. 1997. [56] T. S. Horng, S. M.Wu, and C. Shih, “Electrical modeling of RFIC packages up to 12 GHz,” in Proc. 49th Electron. Comp. Technol. Conf., 1999, pp. 867–712 [57] T. Liang, J. A. Pl′a, P. H. Aaen, and M. Mahalingam, “Equivalent-circuit modeling and verification of metal-ceramic packages for RF and microwave power transistors,” IEEE Trans. Microwave Theory and Tech., vol. 47, pp. 709–714, June. 1999. [58] R. Sturdivant, C. Quan, and J. Wooldridge, “Investigation of MMIC flip chips with sealants for improved reliability without hermeticity,” in IEEE MTT-S Int. Microwave Symp. Dig., 1996, pp. 239-242. [59] E. J. Vardaman and T. Goodman, “Flip chip market trends and infrastructure limitations,” in Int. Electron. Manufact. Symp. Dig., 1997, pp. 37-40. [60] K. Boustedt, “GHz flip-chip—An overview,” in Proc. 48th Electron. Comp. Technol. Conf., 1998, pp. 1280–1285. [61] A. Chandrasekhar, E. Beyne, W. De Raedt, and B. Nauwelaers, “Distributed circuit models for near-CSP interconnects,” in Proc. IEEE 11th Topical Elect. Performance Electron. Packag. Meeting, 2002, pp. 63-66. [62] H. H. M. Ghouz and E. EL-Sharawy, “An accurate equivalent circuit model of flip chip and via interconnects,” IEEE Trans. Microwave Theory and Tech., vol. 44, pp. 2543-2554, Dec. 1996. [63] J. Ryoo, J. Choo, I. H. Park, J. Hong, and J. Lee, “Full wave simulation of flip-chip packaging effects on RFID transponder,” in Proc. IEEE Int. RFID Conf., 2007, pp. 37-40. [64] D. Staiculescu, H. Liang, J. Laskar, and J. Mather, “Full wave analysis and development of circuit models for flip chip interconnects,” in Proc. 7th IEEE Topical Elect. Performance Electron. Packag. Meeting, 1998, pp. 241–244. [65] W. Heinrich, A. Jentzsch, and G. Baumann, “Millimeter-wave characteristics of flip-chip interconnects for multichip modules,” IEEE Trans. Microwave Theory and Tech., vol. 46, no. 12, pp. 2264–2268, Dec. 1998. [66] D. Staiculescu, A. Sutono, and J. Laskar, “Wideband scalable electrical model for microwave millimeter wave flip chip interconnects,” IEEE Trans. Adv. Packag., vol. 24, pp. 255-259, Aug. 2001. [67] A. Jentzsch and W. Heinrich, “Theory and measurements of flip-chip interconnects for frequencies up to 100 GHz,” IEEE Trans. Microwave Theory and Tech., vol. 49, no. 12, pp. 871–878, May 2001. [68] R. J. Pratap, D. Staiculescu, S. Pinel, J Laskar, and G. S. May, “Modeling and sensitivity analysis of circuit parameters for flip-chip interconnects using neural networks,” IEEE Trans. Adv. Packag., vol. 28, pp. 71-78, Feb. 2005. [69] C. S. Patel, P. S. Andry, K. A. Jenkins, B. Dang, R. Horton, R. J. Polastre, and C. K. Tsang, “Characterization of flip chip microjoins up to 40 GHz using silicon carrier,” in Proc. Int. Interconnect Tech. Conf., June 2005, pp. 129-131. [70] U. Preiffer and B. Welch, “Equivalent circuit model extraction of flip-chip ball interconnects based on direct probing techniques,” IEEE Microwave Wireless Comp. Lett., vol. 15, pp. 594-596, Sept. 2005. [71] U. Preiffer and A. Chandrasekhar, ”Characterization of flip-chip interconnects up to millimeter-wave frequencies based on a nondestructive in situ approach,” IEEE Trans. Adv. Packag., vol. 28, pp. 160-167, May 2005. [72] S. K. Lohokare, Z. Lu, C. A. Schuetz, and D. W. Prather, “Electrical characterization of flip-chip interconnects formed using a novel conductive-adhesive-based process,” IEEE Trans. Adv. Packag., vol. 29, pp. 542-547, Aug. 2006. [73] C.-L. Wang, and R.-B. Wu, “Modeling and design for electrical performance of wideband flip-chip transition,” IEEE Trans. Adv. Packag., vol. 26, pp. 385-391, Nov. 2003. [74] N. Iwasaki, F. Ishitsuka, and K. Kato, “High performance flip-chip technique for wide-band modules,” in Proc. IEEE 5th Topical Elect. Performance Electron. Packag. Meeting, 1996, pp. 207–209. [75] W. Heinrich and A. Jentzsch, “Optimization of flip-chip interconnects for millimeter-wave frequencies,” in IEEE MTT-S Int. Microwave Symp. Dig., 1999, pp. 637–640. [76] R. W. Jackson and R. Ito, “Modeling millimeter-wave IC behavior for flipped-chip mounting schemes,” IEEE Trans. Microwave Theory and Tech., vol. 45, pp. 1919-1925, Oct. 1997. [77] A. Chandrasekhar, E. Beyne, W. D. Raedt, and B. Nauwelaers, “Accurate RF electrical characterisation of CSPs using MCM-D thin film technology,” IEEE Trans. Adv. Packag., vol. 27, pp. 203-212, Feb. 2004. [78] D. R. McCann and S. Ha, “Package characterization and development of a flip chip QFN package,” in Proc. 52th Electron. Comp. Technol. Conf., 2002, pp. 365–371. [79] J. Lin, “Chip-package codesign for high-frequency circuits and systems,” IEEE Micro., pp. 24-32, July 1998. [80] A. C. Cangellaris, “Electrical modeling and simulation challenges in chip-package codesign,” IEEE Micro., pp. 50-59, July 1998. [81] A. K. Varma, A. Glaser, and P. D. Franzon, “CAD flows for chip-package coverification,” IEEE Trans. Adv. Packag., vol. 28, pp. 96-101, Feb. 2005. [82] T. Brandtner, “Chip-package codesign flow for mixed-signal SiP designs,” IEEE Trans. Design Test Comput., vol. 23, pp. 196-202, June 2006. [83] G. Nayak and P.R. Mukund, “Chip package co-design of a heterogeneously integrated 2.45 GHz CMOS VCO using embedded passives in a silicon package,” in Proc. 17th Int. VLSI Design Conf., 2004, pp. 627-630. [84] T. Torikka, X. Duo, L.-R. Zheng, E. Tjukanoff, and H. Tenhunen, “Chip-package co-design of a concurrent LNA in system-on-package for multi-band radio applications,” in Proc. 54th Electron. Comp. Technol. Conf., 2004, pp. 1687–1692. [85] X. Duo, L.-R. Zheng, and H. Tenhunen, “Chip-package co-design of common emitter LNA in system-on-package with on-chip versus off-chip passive component analysis,” in Proc. Elect. Performance Electron. Packag., 2003, pp. 55-58. [86] S. Donnay, P. Pieters, K. Vaesen, W. Diels, P. Wambacq, W. De Raedt, E. Beyne, M. Engels, and I. Bolsens, “Chip-package codesign of a low-power 5-GHz RF front end,” Proceedings of the IEEE, Vol. 88, pp. 1583-1597, Oct. 2000. [87] P. Wambacq, S. Donnay, P. Pieters, W. Diels, K. Vaesen, W. De Raedt, E. Beyne, M. Engels, and I. Bolsens, “Chip-package co-design of a 5 GHz RF front-end for WLAN,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., 2000, pp. 318–319. [88] Y. Amin, H. Tenhunen, H. Jamal, L.-R. Zheng, and X. Duo, “Chip-package codesign of receiver front end modules for RF/wireless applications,” in Proc. Wireless Comm. Applied Computational Electromag. Conf., 2005, pp. 767-770. [89] A. Chandrasekhar, S. Stoukatch, S. Brebels, J. Balachandran, E. Beyne, W. D. Raedt, B. Nauwelaers, and A. Poddar, “Characterisation, modelling and design of bond-wire interconnects for chip-package co-design,” in Proc. European Microwave Conf., 2003, pp.301-304. [90] F. Y. Han, J. M. Wu, T. S. Horng, C. C. Tu, R. Chen, and C. H. Chu, “Chip-Package-Board codesign of highly linear 3G-CDMA upconverter modules,” in Proc. 55th Electro. Comp. Technol. Conf., 2005, pp. 528-531. [91] E. Holzman, Essentials of RF and Microwave Grounding, Boston, MA: Artech House, 2006. [92] S. Kumar, M. Vice, H. Morkner and W. Lam, “Enhancement mode GaAs PHEMT LNA with linearity control (IP3) and phased matched mitigated bypass switch and differential active mixer,” in 2003 IEEE MTT-S Int. Microw. Symp. Dig., pp. 1577-1580. [93] C. P. Yue and S. S. Wong, “On-chip spiral inductors with patterned ground shields for Si-based RF ICs,” IEEE J. Solid-State Circuits, vol. 33, pp. 743-752, May 1998. [94] J. N. Burghartz and B. Rejaei, “On the design of RF spiral inductors on silicon,” IEEE Trans. Electron. Dev., vol. 50, pp. 718-729, March 2003. [95] T.-K. Nguyen, C.-H. Kim, G.-J. Ihm, M.-S. Yang, and S.-G. Lee, “CMOS low-noise amplifier design optimization techniques,” IEEE Trans. Microwave Theory and Tech., vol. 52, no.5, pp. 1433-1442, May 2004. [96] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd ed., New York, NY: Cambridge University Press, 2004. [97] B. Razavi, Design of Analog CMOS Integrated Circuits, New York, NY: McGraw-Hill Inc., 2001. [98] S. A. Maas, Noise in Linear and Nonlinear Circuits, Boston, MA: Artech House Inc., 2005. [99] L. Belostotski and J. W. Heslett, “Noise figure optimization of inductively degenerated CMOS LNAs with integrated gate inductors,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, pp. 1409-1422, July 2006. [100] K.-J. Sun, Z.-M. Tsai, K.-Y. Lin, and H. Wang, “A noise optimization formulation for CMOS low-noise amplifiers with on-chip low-Q inductors,” IEEE Trans. Microwave Theory and Tech., vol. 54, pp. 1554-1560, April 2006. [101] P. Andreani and H. Sjöland, ”Noise optimization of an inductively degenerated CMOS low noise amplifier,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 48, pp. 835-841, Sept. 2001 [102] S. A. Maas, Nonlinear Microwave and RF Circuits, 2nd ed., Boston, MA: Artech House Inc., 2003. [103] P. Wambacq and W. Sansen, Distortion Analysis of Analog Integrated Circuits, Boston, MA: Kluwer Academic Publishers, 1998. [104] V. Aparin and L. E. Larson, “Modified derivative superposition method for linearizing FET low-noise amplifiers,” IEEE Trans. Microwave Theory and Tech., vol. 53, no. 2, pp. 571-581, Feb. 2005. [105] S. Ganesan, E. Sánchez-Sinencio, and J. Silva-Martinez, “A highly linear low-noise amplifier,” IEEE Trans. Microwave Theory and Tech., vol. 54, no. 12, pp. 4079-4085, Dec. 2006. [106] G. Gramegna, M. Paparo, P. G. Erratico, and P. D. Vita, “A sub-1-dB NF 2.3-kV ESD-protected 900-MHz CMOS LNA,” IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1010-1017, July 2001. [107] UE Radio Transmission and Reception, 3GPP Standard 25.101 (V5.3.0), 2002. [108] A. Springer, L. Maurer, and R. Weigel, “RF system concepts for highy integrated RFICs for W-CDMA mobile radio terminals,” IEEE Trans. Microwave Theory and Tech., vol. 50, pp. 254-267, Jan. 2002. [109] G. Jue, “3GPP W-CDMA systems: design and testing,” IEEE Microwave Magazine, pp. 56-64, June 2002. [110] D. S. Malhi, L. E. Larson, D. Wang, C. Demirdag, and V. Pereira, “SiGe W-CDMA transmitter for mobile terminal application,” IEEE J. Solid-State Circuits, vol. 38, pp. 1570-1574, Sept. 2003. [111] T. J. Ellis, “A modified feed-forward technique for mixer linearization,” in IEEE MTT-S Int. Microwave Symp. Dig., 1998, pp. 1423-1426. [112] B. A. Xavier. (2002, Sept. 7). A shunt feedback technique for improving the dynamic range of a balanced mixer. [Online]. Available: http://www.rfengineer.net/rfic.htm [113] V. Aparin and C. Persico, “Effects of out-of-band terminations on intermodulation distortion in common-emitter circuits,” in IEEE MTT-S Int. Microwave Symp. Dig., 1999, pp. 977-980. [114] L. Sheng and L. E. Larson, “An Si-SiGe BiCMOS direct-conversion mixer with second-order and third-order nonlinearity cancellation for WCDMA applications,” IEEE Trans. Microwave Theory and Tech., vol. 51, pp. 2211-2220, Nov. 2003. [115] B. Gilbert, “The micromixer: a highly linear variant of the Gilbert mixer using a bisymmetric Class-AB input stage,” IEEE J. Solid-State Circuits, vol. 32, pp. 1412-1423, Sept. 1997. [116] Q. Wu, H. Xiao, and F. Li, "Linear RF power amplifier design for CDMA signals: a spectrum analysis approach," Microwave J., vol. 41, pp. 22-40, Dec. 1998. [117] J. S. Ko, J.K. Kim, B. K. Ko, D. B. Cheon, and B. H. Park, "Enhanced ACPR technique by class AB in PCS driver amplifier," in Proc. IEEE Int. VLSI CAD Conf., 1999, pp. 376-379. [118] G. D. Vendelin, A. M. Pavio, and U. L. Rohde, Microwave Circuit Design Using Linear and Nonlinear Techniques, 2nd ed., Hoboken, NJ: John Wiley & Sons Inc., 2005. [119] C. Toumazou, G. Moschytz, and B. Gilbert, Trade-Offs in Analog Circuit Design, Dordrecht, Netherlands: Kluwer Academic Publishers, 2002. [120] J. C. Pedro and N. B. Carvalho, Intermodulation Distortion in Microwave and Wireless Circuits, Norwood, MA: Artech House Inc., 2003.
|