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研究生:劉宜政
研究生(外文):Yi-cheng Liu
論文名稱:使用動態閘極偏壓之混合電壓共容輸出入單元與次三倍VDD大範圍混合電壓共容輸出入單元
論文名稱(外文):Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3×VDD Wide Range Mixed-Voltage-Tolerant I/O Cell
指導教授:王朝欽
指導教授(外文):Chua-Chin Wang
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:76
中文關鍵詞:輸出入單元混合電壓共容動態閘極偏壓次3倍VDD
外文關鍵詞:I/O cellMixed-Voltage-TolerantDynamic BiasingSub 3×VDD
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本論文包含兩研究主題,使用動態偏壓之混合電壓輸出入單元與次3倍VDD大範圍雙向共容輸出入單元

第一個主題探討一混合電壓輸出入單元,以TSMC 0.35 μm製程實現。本設計藉由一低靜態功率消耗之動態閘極偏壓產生電路,提供三組不同邏輯0準位與邏輯1準位之偏壓,使輸出級電路能在傳輸及接收時有效導通及關閉,避免任何閘極氧化層過度應力與漏電流問題。本設計也提出一改良式的輸出級來加強傳輸低壓時的電流驅動能力,使輸出波形工作責任週期達到50%,將可適用於不同電壓介面應用。

第二個主題探討一次3倍VDD大範圍雙向共容輸出入單元,由TSMC 0.18 μm製程實現。其藉由一新型動態閘極偏壓產生電路與PAD電壓偵測電路,提供輸出級適當之閘極偏壓。本設計同時提出一新式閘極追蹤電路與浮動N井電路解決過壓與漏電流問題,並消除輸出級PMOS基體效應,可達到傳輸與接收次三倍VDD電壓之輸出入單元。
The thesis is composed of tow topics: a fully bidirectional mixed- voltage-tolerant I/O cell using a new output stage circuit and a sub-3×VDD wide range fully bidirectional mixed-voltage-tolerant I/O cell.

The first topic discloses a mixed-voltage-tolerant I/O cell implemented using 2P4M 0.35 μm CMOS process, which uses a low static power dynamic gate bias generator providing three different logic voltage levels to the output stage to avoid gate oxide reliability and leakage current. The design also reveals a new output stage circuit, which enhances the output current to resolve the poor driving capability caused by the slow mobility and body effect of the stacked PMOS.

The second topic shows a sub-3×VDD wide range fully bidirectional mixed-voltage-tolerant I/O cell using 1P6M 0.18 μm CMOS process, which employs a new dynamic gate bias generator and a PAD voltage detector to provide appropriate gate biases. The design includes a new gate tracking circuit and a floating N-well circuit to avoid gate oxide reliability and leakage current, which relaxes the body effect at the output PMOS.
致謝 i
摘要 ii
Abstract iii
目錄 iv
圖目錄 vii
表目錄 x
第一章 概論 1
1.1 研究動機 1
1.2 關技術與文獻探討 2
1.2.1 傳統輸出輸入單元 2
1.2.2 傳統混合電壓輸出輸入單元 4
1.3 論文大綱 6
第二章 使用動態閘極偏壓之混合電壓輸出入單元 7
2.1 簡介 7
2.2 電路架構與設計 7
2.3 電路原理 9
2.3.1 前置驅動級電路 9
2.3.2 輸出級 11
2.3.3 動態閘極偏壓產生器 12
2.3.4 輸入級 17
2.3.5 浮動N井電路 18
2.3.6 閘極追蹤電路 18
2.3.7 ESD保護電路 19
2.4 電路模擬與預計規格 20
2.4.1 電路模擬結果 20
2.4.2 預計規格 24
2.4.3 效能比較 25
2.5 晶片佈局 25
2.6 晶片實作與量測結果 27
2.6.1 靜電放電防護能力量測 30
2.6.2 晶片量測結果討論 31
第三章 次3倍VDD大範圍共容輸出入單元 32
3.1 簡介 32
3.2 電路架構與設計 33
3.3 電路原理 34
3.3.1 高電壓偵測電路 34
3.3.2 PAD電壓偵測電路 37
3.3.3 動態閘極偏壓產生器 39
3.3.4 浮動N井電路 49
3.3.5 閘極追蹤電路 51
3.3.6 輸入級 52
3.3.7 輸出級 53
3.4 電路模擬與預計規格 54
3.4.1 電路模擬結果 54
3.4.2 預計規格 58
3.4.3 效能比較 59
3.5 晶片佈局 59
3.6 結果與討論 60
第四章 研究成果與結論 61
參考文獻 62
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