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[1] www.itrs.net [2] C.-H. Chuang, and M.-D. Ker, “Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-um CMOS technology,” in Proc. of IEEE Int. Symp. on Circuits and Systems, 2004, vol. 2, pp. 577-580, May 2004. [3] T. Furukawa, D. Turner, S. Mittl, M. Maloney, R. Serafin, W. Clark, L. Longenbach, and J. Howard, “Accelerated gate-oxide breakdown in mixed- voltage I/O buffers,” in Proc. of IEEE Int. Symp. on Reliability Physics pp. 169-173, Apr. 1997. [4] A.-J. Annema, G. J. G. M. Geelen, and P. C. de Jong, “5.5-V I/O in a 2.5-V 0.25-μm CMOS Technology,” IEEE J. of Solid-state Circuits, vol. 36, no. 3, pp. 528-538, Mar. 2001. [5] M.-D. Ker, and S.-L. Chen, “Design of mixed-voltage I/O buffer by using NMOS-blocking technique,” IEEE J. of Solid-State Circuits, vol. 41, no. 10, pp. 2324–2333, Oct. 2006. [6] G. P. Singh and R. Salem, “High-voltage-tolerant I/O buffers with low-voltage CMOS process,” IEEE J. of Solid-State Circuits, vol. 34, no. 11, pp. 1512-1525, Nov. 1999. [7] M.-D. Ker, and C.-H. Chuang, “Electrostatic discharge protection for design for mixed-voltage CMOS I/O buffers,” IEEE J. of Solid-State Circuits, vol. 37, no. 8, pp. 1046-1055, Aug. 2002. [8] M.-D. Ker, S.-L. Chen, and C.-S. Tsai, “Overview and design of mixed- voltage I/O buffers with low-voltage thin-oxide CMOS transistors,” IEEE Trans. on Circuits and Systems-I, vol. 53, no. 9, pp. 1934-1945, Sept. 2006. [9] M.-D. Ker, and S.-L. Chen, “Mixed-voltage I/O buffer with dynamic gate-bias circuit to achieve 3×VDD input tolerance by using 1×VDD devices and single VDD supply,” in tech. digest of 2005 IEEE Int. Solid-State Circuits Conf., vol. 1, pp. 524-614, Feb. 2005. [10] G. Liu, Y. Wang, and S. Jia, “A New design of mixed-voltage I/O buffers with low-voltage-thin-oxide CMOS process,” in Proc. of Int. Conf. on ASIC, pp. 201-204, Oct. 2007. [11] M. J. M. Pelgrom, and E. C. Dijkmans, “A 3/5 V compatible I/O buffer,” IEEE J. of Solid-State Circuits, vol. 30, no. 7, pp. 823-825, July 1995. [12] M.-D. Ker, and K.-H. Lin, “Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations,” IEEE Trans. on Circuits and Systems-I , vol. 53, no. 2, pp. 235-246, Feb. 2006. [13] M.-D. Ker, K.-H. Lin, and C.-H. Chuang, “On-chip ESD protection design with substrate- triggered technique for mixed-voltage I/O circuits in sub-quarter-micron CMOS process,” IEEE Trans. on Electron Devices, vol. 51, no. 10, pp. 1628-1635, Oct. 2004. [14] M.-D. Ker, and H.-C. Hsu, “ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit,” IEEE Trans. on Circuits and Systems-I, vol. 52, no. 1, pp. 44-53, Jan. 2005. [15] M.-D. Ker, and C.-S Tsai, “Design of 2.5V/5V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic n-well bias circuit,” in Proc. of IEEE Int. Symp. on Circuits and Systems, vol. 5, no. 5, pp. 97-100, May 2003. [16] M.-D. Ker, and C.-H. Chang, “Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface ,” IEEE Electron Device Letters, vol. 23, no. 6, pp. 363-365, June 2002. [17] M. Takahashi, T. Sakurai, K. Sawada, K. Nogami, M. Ichida, and K. Matsuda, “3.3 V-5 V compatile I/O circuit without thick gate oxide,” in Proc. of IEEE Custom Integrated Circuits Conf., pp. 23.3.1-23.3.4, 1992. [18] H. Sanchez, J. Siegel, C. Nicoletta, J. P. Nissen, and J. Alvarez, “A versatile 3.3/2.5/1.8-V CMOS I/O driver built in a 0.2-μm, 3.5-nm Tox, 1.8-V CMOS technology,” IEEE J. of Solid-State Circuits, vol. 34, no. 11, pp. 1501-1511, Nov. 1999. [19] T.-J. Lee, T.-Y. Chang, and C.-C. Wang, “Mixed-voltage-tolerant I/O buffer design,” in Proc. of Int. Symp. on Integrated Circuits 2007, pp. 596-599, Sept. 2007. [20] S.-L. Chen, and M.-D. Ker, “An output buffer for 3.3-V applications in a 0.13-μm 1/2.5-V CMOS process,” IEEE Trans. on Circuits and Systems-II: Express Brief, vol. 54, no. 1, pp. 14-18, Jan. 2007. [21] T.-J. Lee, W.-C. Chang, and C.-C. Wang, “Mixed-voltage-tolerant I/O buffer using a clamping dynamic gate bias Generator,” in Proc. of 2007 IEEE Region 10 Conf. - TENCON 2007, Nov. 2007, pp. 1-4. [22] M.-D. Ker, T.-M. Wang, and F.-L. Hu, “Design on mixed-voltage I/O buffers with slew-rate control in low-voltage CMOS process,” in Proc. of IEEE International Conference on Electronics, Circuits and Systems, Aug. 2008, pp. 1047-1050. [23] T.-J. Lee, Y.-C. Liu, and C.-C. Wang, “1.8 V to 5.0 V mixed–voltage- tolerant I/O buffer with 54.59% output duty cycle,” in Proc. of IEEE Int. Symp. on VLSI Design, Automation and Test 2008, Apr. 2008, pp. 93-96.
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