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研究生:曾鴻任
研究生(外文):Hung-Jen Tseng
論文名稱:具有阻隔氧化層與本體縛點之薄膜電晶體與非揮發性記憶體之製作與探討
論文名稱(外文):Fabrication and Characterization of Polycrystallin Silicon Thin-Film Transistor and Nonvolatile Memory with Block Oxide and Body-tie
指導教授:林吉聰
指導教授(外文):Jyi-Tsong Lin
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:70
中文關鍵詞:薄膜電晶體非揮發性記憶體
外文關鍵詞:SONOSThin-Film Transistor
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在此論文中,我們提出了擁有自我對齊且具有阻隔氧化層與本體縛點之金氧半場效電晶體與非揮發性記憶的結構。
在金氧半場效電晶體方面,我們企圖以阻隔氧化層來抑制電荷共享效應,減低在微縮時短通道效應對電晶體所造成的影響,並以阻隔氧化層來阻擋閘極與源╱汲極間的空乏區向通道部分擴散,減少漏電流與功率消耗的損失;而本體縛點之結構則能有效改善電晶體之溫度,降低自我加熱效應之問題產生。結果發現,具有阻隔氧化層與本體縛點之電晶體結構確實擁有不錯的特性,如小的 DIBL 、較傾斜的次臨限斜率、以及高的電流On / Off比等特性,以應證能降低短通道效應之影響。
在非揮性記憶體方面,由於傳統的 SONOS 閘極穿透氧化層(Tunneling oxide)厚度太薄,在低於三奈米時會使得通道上的電洞因為直接穿透(Direct tunneling)至氮化矽,使得穿透進來的電洞與氮化矽內部捕陷層(Trap layer)的電子產生中和進而使記憶體內部的資料消失而產生漏電的現象,造成資料保存時間下降(Data retention)或是資料可寫入的次數(Endurance)減少;然而如果為了改善其漏電的現象而將穿透氧化層厚度增厚,反而會使得能障提高,造成抹除速度下降。因此在結構上,我們企圖在基板上引入本體縛點與阻隔氧化之層結構,並在不減少閘極穿透氧化層的厚度以及不改變閘極結構與材料的情況下,能有更優越的閘極控制力,增加開關電流比(On / Off ratio),擁有較陡峭的次臨界導通斜率SS(subthreshold slope),使得元件在進入寫入╱抹除(Program╱Erase)的操作時,能具有更高的效率,比一般標準結構的SONOS能更為穩定,增加元件的可靠度與穩定性。
第一章 導論 -------------------------------------------------- 7
1-1矽覆絕緣金氧半場效電晶體簡介------------------------------ 7
1-2非揮發性記憶體簡介---------------------------------------- 11
第二章 元件設計與製程 ----------------------------------------- 18
2-1元件設計-------------------------------------------------- 18
2-1-1 具有阻隔氧化層與本體縛點之金氧半場效電晶體
(bSPIFET) --------------------------------------- 18
2-1-2具有阻隔氧化層與本體縛點之非揮發性記憶體
(bSPISONOS)------------------------------------- 20
2-2元件ISE TCAD FLOOPS 2-D模擬設計------------------------- 22
2-2-1具有阻隔氧化層與本體縛點之金氧半場效電晶體
(bSPIFET)---------------------------------------- 23
2-2-2具有阻隔氧化層與本體縛點之非揮發性記憶體
(bSPISONOS)------------------------------------- 25
2-3實際製程 ------------------------------------------------ 25
2-3-1實際製程考量------------------------------------------- 28
2-3-2實際製程----------------------------------------------- 30
第三章 結果與討論 -------------------------------------------- 32
第四章 結論 -------------------------------------------------- 51
第五章 未來發展 ---------------------------------------------- 52
參考文獻 ----------------------------------------------------- 53
附錄 :
圖目錄

圖 1.1:bFDSOI之結構示意圖 --------------------------------- 09
圖 1.2:Re S/D UTBSOI之結構示意圖 -------------------------- 10
圖 1.3:PiFET之結構示意圖 ---------------------------------- 10
圖 1.4:浮動閘極元件與電荷能陷儲存元圖 ---------------------- 12
圖1.5:浮動閘極元件耦合干擾 --------------------------------- 13
圖1.6:過薄的穿透氧化層造成漏電 ----------------------------- 13
圖1.7:SONOS memory結構示意圖 ----------------------------- 14
圖 1.8:Twin-SONOS之結構示意圖 ----------------------------- 15
圖 1.9:TANOS之結構示意圖 -------------------------------- 16
圖 1.10:BE-SONOS之結構示意圖 ------------------------------ 17
圖 2.1:bSPIFET的元件結構示意圖------------------------------ 19
圖 2.2:bSPISONOS的元件結構示意圖--------------------------- 21
圖 2.3:bSPIFET使用ISE TCAD FLOOPS軟體模擬簡易製程步驟圖--- 24
圖 2.4:bSPISONOS使用ISE TCAD FLOOPS軟體模擬簡易製程步驟圖 27
圖 2.5:實際製程之重要流程步驟--------------------------------- 29
圖 2.6:實際製程之主要步驟流程圖 ------------------------------ 31
圖 3.1:bSPIFET與對照組元件的切面圖 -------------------------- 33
圖 3.2:bSPIFET與對照組元件的輸入特性曲線--------------------- 33
圖 3.3:bSPIFET與對照組元件的臨限電壓特性圖-------------------- 35
圖 3.4:bSPIFET與對照組元件的臨限電壓特性圖-------------------- 35
圖 3.5:bSPIFET與對照組元件的DIBL特性圖---------------------- 36
圖 3.6:bSPIFET與對照組元件的輸出特性曲線---------------------- 36
圖 3.7:bulk MOSFET在VGT=0.2V的晶格溫度分佈圖---------------- 38
圖 3.8:bSPIFET在VGT=0.2V的晶格溫度分佈圖--------------------- 38
圖 3.9:UTBSOI在VGT=0.2V的晶格溫度分佈圖--------------------- 39
圖 3.10:bulk MOSFET在VGT=0.2V的碰撞游離數目分佈圖------------40
圖 3.11:bSPIFET在VGT=0.2V的碰撞游離數目分佈圖---------------- 40
圖 3.12:UTBSOI在VGT=0.2V的碰撞游離數目分佈圖---------------- 41
圖 3.13:bSPIFET與對照組元件的串聯電阻特性圖------------------- 42
圖 3.14:不同的阻隔氧化層高度的電性圖--------------------------- 42
圖 3.15:L-Edit之光罩圖---------------------------------------- 43
圖 3.16:電子顯微鏡檢視圖-------------------------------------- 45
圖 3.17:光學顯微鏡檢視圖-------------------------------------- 45
圖 3.18:bSPIFET之穿透式電子顯微鏡(TEM)元件剖面圖---------- 46
圖 3.19:bSPISONOS之穿透式電子顯微鏡(TEM)元件剖面圖-------- 46
圖 3.20:4156量測時之簡圖---------------------------------------47
圖 3.21:線性區輸入特性曲線IDS-VGS ------------------------------48
圖 3.22:線性區轉導特性曲線------------------------------------- 48
圖 3.23:飽和區輸入特性曲線IDS-VGS------------------------------ 49
圖 3.24:輸出特性曲線IDS-VDS------------------------------------ 49
圖 3.25:不同溫度下的線性區輸入特性曲線IDS-VGS ------------------ 50
圖 3.26:不同溫度下的線性區轉導特性曲線------------------------- 50
[1] Vinet, M.; Poiroux, T.; Widiez, J.; Lolivier, J.; Previtali, B.; Vizioz, C.; Guillaumot, B.; Le Tiec, Y.; Besson, P.; Biasse, B.; Allain, F.; Casse, M.; Lafond, D.; Hartmann, J.-M.; Morand, Y.; Chiaroni, J.; Deleonibus, S. “ Bonded planar double-metal-gate NMOS transistors down to 10 nm”Electron Device Letters, IEEE Volume 26, Issue 5, May 2005 Page(s): 317 – 319.
[2] Zhao, H. Agrawal, N. Javier, R. Rustagi, S.C. Jurczak, M. Yeo, Y.-C. Samudra, G.S. “Simulation of Multiple Gate FinFET Device Gate Capacitance and Performance with Gate Length and Pitch Scaling”Simulation of Semiconductor Processes and Devices, 2006 International Conference on Publication Date: 6-8 Sept. 2006 On page(s): 252-255.
[3] Mori, K. “Vertical MOS transistor with threshold voltage adjustment”, Electronics Manufacturing Technology Symposium, 1999. Twenty-Fourth IEEE/CPMT Volume , Issue , 1999 Page(s):245 – 248
[4] Schulz, T.; Rosner, W.; Risch, L.; Langmann, U. “50-nm vertical sidewall transistors with high channel dopingconcentrations”, Electron Devices Meeting, 2000. IEDM Technical Digest. International Volume , Issue , 2000 Page(s):61 – 64.
[5]J-P Colinge,“Silicon-On-Insulator Technology:Materials toVLSI,”Kluwer Academic Publishers, Massachusetts.
[6]M. Valdinoci, L. Colalongo, G. Baccarani, G. Fortunato, A. Pecora, and I. Policicchio, “Floating body effects in polysilicon thin-film transistors,” IEEE Trans. on Electron Devices, vol. 44, p2234–2241, Dec. 1997.
[7]Krishnan, S.; Fossum, J.G, “Grasping SOI floating-body effects,” Circuits and Devices Magazine, IEEE Volume 14, Issue 4, July 1998, Page(s):32 – 37.
[8] Bae, G.J.; Choe, T.H.; Kim, S.S.; Rhee, H.S.; Lee, K.W.; Lee, N.I.; Kim, K.D.; Park, Y.K.; Kang, H.S.; Kim, Y.W.; Fujihara, K.; Kang, H.K.; Moon, J.T “A novel SiGe-inserted SOI structure for high performance PDSOI CMOSFETs,” IEEE Electron Devices Meeting, Dec. 2000 Page(s):667 – 670.
[9] Jyi-Tsong Lin; Yi-Chuen Eng; Kuo-Dong Huang; Tai-Yi Lee; Kao-Cheng Lin; “A Novel FDSOI MOSFET with Block Oxide Enclosed Body” Integrated Circuit Design and Technology, 2006. Page(s):1 – 4.
[10] Yi-Chuen Eng; Jyi-Tsong Lin; “Self-aligned Block Oxide Process for bFDSOI Devices” Integrated Circuit Design and Technology, 2007. Page(s):1 – 4.
[11] Zhikuan Zhang; Shengdong Zhang; Mansun Chan; “Self-Align Recessed Source Drain Ultrathin Body SOI MOSFET” IEEE ELECTRON DEVICE LETTERS, vol. 25, NO. 11, NOVEMBER 2004.
[12] Wei Ke; Xu Han; Dingyu Li; Xiaoyan Liu; Ruqi Han; Shengdong Zhang; “Recessed Source/Drain for Scaling SOI MOSFET to the Limit” Solid-State and Integrated Circuit Technology, Oct. 2006 Page(s):84 – 86.
[13] Zhikuan Zhang; Shengdong Zhang; Mansun Chan; “Recessed source/drain for sub-50 nm UTB SOI MOSFET” SEMICONDUCTOR SCIENCE AND TECHNOLOGY, vol. 25, NO. 11, NOVEMBER 2007 Page(s):577 – 583.
[14] Kyoung Hwan Yeo; Chang Woo Oh; Sung Min Kim; Min Sang Kim; Chang Sub Lee; Sung Young Lee; Sang Yeon Han; Eun Jung Yoon; Hye Jin Cho; Doo Youl Lee; Byung Moon Yoon; Hwa Sung Rhee; Byung Chan Lee; Jeong Dong Choe; Ilsub Chung; Donggun Park; Kinam Kim; “A Partially Insulated Field-Effect Transistor (PiFET) as a Candidate for Scaled Transistors”, IEEE Electron Devices Lett., vol. 25, pp. 387-389, Jun. 2004.
[15] Miyamoto, M.; Nagai, R.; Nagano, T.; “Pseudo-SOI: P-N-P-channel-doped bulk MOSFET for low-voltage high-performance applications” Electron Devices Meeting, 1998.6-9 Dec. 1998 Page(s):411 – 414.
[16] Chih-Yuan Lu, Tao-Cheng Lu, and Rich Liu, T.; “NON-VOLATILE MEMORY TECHNOLOGY - TODAY AND TOMORROW” International Project Finance Association, 2006 Page(s):18-23.
[17] Sheng-Chih Lai; Hang-Ting Luea; Jung-Yu Hsieh; Ming-Jui Yang; Yan-Kai Chiou; Chia-Wei Wu; Tai-Bor Wu; Guang-Li Luo; Chao-Hsin Chien; Erh-Kun Lai; Kuang-Yeu Hsieh; Rich Liu; Chih-Yuan Lu; “A Study on the Erase and Retention Mechanisms for MONOS, MANOS, and BE-SONOS Non-Volatile Memory Devices” VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on 23-25 April 2007 Page(s):1 – 2.
[18] White, M.H.; Adams, D.A.; Bu, J.; “on the go with SONOS” Circuits and Devices Magazine, Volume 16, Issue 4, July 2000 Page(s):22 – 31.
[19] Chung-Yu Chiang, “Fabrication and Characterization of Double-Gated Nanowire SONOS Devices” National Chiao-Tung University Electronic Engineering, July 2008.
[20] Byung Yong Choi; Choong-Ho Lee; Yong Kyu Lee; Hyungcheol Shin; Jong Duk Lee; Byung-Gook Park; Dong-Won Kim; Suk-Kang Sung; Se Hoon Lee; Byung-Kyu Cho; Tae-Yong Kim; Eun Suk Cho; Jong Jin Lee; Donggun Park; “Investigation of Lateral Charge Distribution of 2-bit SONOS Memory Devices Using Physically Separated Twin SONOS Structure” Microelectronic Test Structures, 20066-9 March 2006 Page(s):47 – 50.
[21] Byung Yong Choi; Byung-Gook Park; Yong Kyu Lee; Suk Kang Sung; Tae Yong Kim; Eun Suk Cho; Hye Jin Cho; Chang Woo Oh; Sung Hwan Kim; Dong Won Kim; Choong-Ho Lee; Donggun Park; “Highly scalable and reliable 2-bit/cell SONOS memory transistor beyond 50nm NVM technology using outer sidewall spacer scheme with damascene gate process” VLSI Technology, 2005. 14-16 June 2005 Page(s):118 – 119.
[22] Yong Kyu Lee; Ki Whan Song; Jae Woong Hyun; Jong Duk Lee; Byung-Gook Park; Sung Taeg Kang; Jeong Dong Choe; Sang Yeon Han; Jeong Nam Han; Sung Woo Lee; Kwon, O.I.; Chung, C.; Donggun Park; Kinam Kim; “Twin SONOS Memory With 30-nm Storage Nodes Under a Merged Gate Fabricated With Inverted Sidewall and Damascene Process” Electron Device Letters, IEEE Volume 25, Issue 5, May 2004 Page(s):317 – 319.
[23] Chang Hyun Lee; Kyung In Choi; Myoung Kwan Cho; Yun Heub Song,Kyu Cham Park; and Kinam Kim; “A Novel SONOS Structure of Si02/SiN/A1203 with TaN metal gate for multi-giga bit flash memeries” Electron Devices Meeting, 2003 Page(s):613 – 616.
[24] Yoocheol Shin; Jungdal Choi; Changseok Kang; Changhyun Lee; Ki-Tae Park; Jang-Sik Lee; Jongsun Sel; Kim, V.; Byeongin Choi; Jaesung Sim; Dongchan Kim; Hag-ju Cho; Kinam Kim; “A Novel NAND-type MONOS Memory using 63nm Process Technology for Multi-Gigabit Flash EEPROMs” Electron Devices Meeting, 2005. Dec. 2005 Page(s):327 – 330.
[25] Hang-Ting Lue; Szu-Yu Wang; Erh-Kun Lai; Yen-Hao Shih; Sheng-Chih Lai; Ling-Wu Yang; Kuang-Chao Chen; Ku, J.; Kuang-Yeu Hsieh; Rich Liu; Chih-Yuan Lu; “ BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability” Electron Devices Meeting, 2005. 5-5 Dec. 2005 Page(s):547 - 550.
[26] Sheng-Chih Lai; Hang-Ting Lue; Ming-Jui Yang; Jung-Yu Hsieh; Szu-Yu Wang; Tai-Bor Wu; Guang-Li Luo; Chao-Hsin Chien; Erh-Kun Lai; Kuang-Yeu Hsieh; Liu, R.; Chin-Yuan Lu; “Highly Reliable MA BE-SONOS (Metal-A1203 Bandgap Engineered SONOS)Using a SiO2 Buffer Layer” Non-Volatile Semiconductor Memory Workshop, 2007 22nd IEEE 26-30 Aug. 2007 Page(s):88 – 89.
[27] Min-Ta Wu; Hang-Ting Lue; Kuang-Yeu Hsieh; Rich Liu; Chih-Yuan Lu; “Study of the Band-to-Band Tunneling Hot-Electron (BBHE) Programming Characteristics of p-Channel Bandgap-Engineered SONOS (BE-SONOS)” Electron Devices, IEEE Transactions on Volume 54, Issue 4, April 2007 Page(s):699 – 706.
[28] Szu-Yu Wang; Hang-Ting Lue; Erh-Kun Lai; Ling-Wu Yang; Tahone Yang; Kuang-Chao Chen; Jeng Gong; Kuang-Yeu Hsieh; Rich Liu; Chih Yuan Lu; “Reliability and Processing Effects of Bandgap Engineered SONOS (BE-SONOS) Flash Memory” Reliability physics symposium, 2007. proceedings. 45th annual. ieee international 15-19, April 2007 Page(s):171 – 176.
[29] Hang-Ting Lue; Szu-Yu Wang; Erh-Kun Lai; Kuang-Yeu Hsieh; Rich Liu; Chih Yuan Lu; “A BE-SONOS (Bandgap Engineered SONOS) NAND for Post-Floating Gate Era Flash Memory” VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on 23-25 April 2007 Page(s):1 – 2.
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