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研究生:蘇明全
研究生(外文):Ming-chiuan Su
論文名稱:用於連續時間濾波器的差分模式自動調協電路
論文名稱(外文):An Automatic Tuning Circuit for Differential-Mode Continuous-Time Filter
指導教授:高家雄
指導教授(外文):Chia-Hsiung Kao
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:英文
論文頁數:56
中文關鍵詞:調協電路濾波器
外文關鍵詞:tuning circuitfilter
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此篇論文提出一個自動調協電路,此電路為針對補償因製程、供應電壓、溫度等變異所造成濾波器的頻寬誤差。

我們以一個可調式轉導放大器及一個電容來形成一個單一時間常數電路,當輸入一個參考時脈至此電路,其輸出端可產生一個可控制延遲時間的時脈,此調協電路即是利用固定輸出時脈延遲時間,來調協濾波器的頻寬。

這種單一時間常數電路的設計比較簡單,且有較小的晶片面積。所有電路
設計參數鈞以TSMC 2P4M 0.35微米之混合信號製程參數為基礎,全電路之供應電壓為3伏特。由模擬結果顯示,當濾波器操作在供應電壓變動10%、溫度(-20℃到70℃)和五種SPICE製程模組的情況下,此種調協電路可將濾波器的頻寬誤差控制在7%內。
This thesis presents an automatic tuning circuit that it is focused on compensation for the filter’s frequency error resulting from the variation of fabrication process, supply voltage and temperature.
We utilize a tunable operational transconductance amplifier and a capacitor to form a single-time constant circuit (STC). When we input a reference signal to this circuit, the output of STC circuit can produce a controllable delay time clock. The tuning circuit uses the constant delay time to tune the frequency of the filter.
The design of the STC circuit is simple and it has less chip area. All circuits are designed by using the parameters of TSMC 0.35um mixed signal process, and the supply voltage is 3V. The simulation result shows that the filter’s 3-dB frequency error can be controlled by less than 7% as the filter is under the condition of over a range of supply voltages(±10%), operating temperatures(-20 ℃to 70℃ ) and five models of SPICE model.
Chapter 1
Introduction 1
1.1 Introduction 1
1.2 Thesis Overview 3
Chapter 2
Previous Tuning Methods 4
2.1 The Automatic Frequency Controller 4
2.2 Frequency Tuning Circuit 6
2.2.1 Voltage Controlled Constant Gm Tuning Circuit 6
2.2.2 Current Controlled Constant Gm Tuning Circuit 7
2.2.3 Sinusoidal Oscillator Based PLL Frequency Tuning 7
2.2.4 PLL with Charge-Pump Phase Comparator 9
Chapter 3
The Proposed Tuning Circuit and the Fifth-order Gm-C Filter 10
3.1 The Operation of Proposed Tuning Mechanism 10
3.1.1 The Block Diagram of Tuning Circuit 10
3.1.2 STC Circuit 11
3.1.3 Delay Time Analysis 12
3.1.4 The Tunable OTA [9]: 16
3.1.5 CMFB Circuit 18
3.2 The Structure of Proposed Tuning Circuit 19
3.2.1 Voltage Comparator: 20
3.2.2 Phase Detector 25
3.2.3 Charge Pump 26
3.2.4 Low-Pass Filter 27
3.3 Design of Gm-C Filter 28
3.3.1 Basic Filter Theorem 28
3.3.2 The Gm-C Filter 29
3.3.2.1 OTA’s Simple Circuit 29
3.3.2.2 The 5th –order LP Butterworth Gm-C Filter 32
Chapter 4
Simulation and Measurement Result 37
4.1 Simulation Result 37
4.1.1 Gm-C Filter Simulation Result 38
4.1.1.1 Without Automatic Tuning Circuit 38
4.1.1.2 With Automatic Tuning Circuit 38
4.2 Measurement Result and Layout 41
4.2.1 Chip Features and Layout 41
4.2.2 Measurement Result 43
Chapter 5
Conclusions 46
Reference 47
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