臺灣博碩士論文加值系統

標準IEEE 802.15.4 作為一個低速近身無線網路，特色是低功率、低成本，用於短距離或室內傳輸。
本文中，我將依照IEEE 802.15.4–2006 其中915MHz振幅相位調變的規格，將整個完整基頻端的傳送與接收機演算法設計出來，並依其結果量化、硬體程式化。在本文中，我們將依序介紹演算法設計、量化與硬體架構、模擬圖與實際量測結果，最後再提出結論以及可改進的方向。
在演算法流程中，我在接收機部份提出了一個新的去除多重序列干擾Table以取代標準中原有的Table，效能改進了0.2~0.4dB，整體演算在最大載波頻率偏移與最大取樣時間偏移的環境下，效能與完美接收機相差1.5dB，量化硬體化之後效能與我的演算法相差約1.5dB，並在完成硬體程式撰寫與模擬後向國家晶片中心提出0.18 CMOS製程的下線申請。

The IEEE 802.15.4 is defined as a Low-Rate Wireless Personal Area Network, which is also called ZigBee. The characteristics of ZigBee are low power consumption for battery life, extremely low cost, short-range operation.
According to 915 MHz Amplitude Shift Keying Modulation part of IEEE 802.15.4 – 2006, we designed transmitter and receiver in base band part. In the later article, we will introduce my algorithm design, the Quantization and the Architecture in hard- ware implementation, the simulations, and the final verifying work of the layout that we did. Finally, we make a conclusion of this thesis, and we bring up the possible improvement in this design.
In my algorithm of the ZigBee receiver, I fined a new table to replace the original table of spec IEEE 802.15.4 to solve multi-sequence interference, which can improve the performance about 0.2 to 0.4dB.
My algorithm is lower 1.5dB than the Ideal receiver, which simulate in none carrier frequency offset (CFO) and none sample time offset, but both of mine are biggest. Then, my architecture implementation in hardware is lower about 1.5dB than my algorithm.
Completed the hardware circuit design and simulations, I applied for a layout in 0.18-um CMOS technology.

目錄
第一章 序論…………………………………………………………………………1
1.1 導論…………………………………………………………………………1
1.2 研究動機……………………………………………………………………1
1.3 論文架構簡述………………………………………………………………2
第二章 IEEE 802.15.4 通訊協定簡介……………………………………………..3
2.1 IEEE 802.15.4 概述………………………………………………………..3
2.1.1 特性描述……………………………………………………………..3
2.1.2 裝置介紹……………………………………………………………..3
2.1.3 網路拓樸形式………………………………………………………..4
2.2 實體層介紹……………………………………………………………….....5
2.2.1 實體層各模式操作簡介……………………………………………..5
2.2.2 封包格式……………………………………………………………..6
2.2.3 敏感度……………...………………………………………………...6
2.3 振幅偏移調變模式介紹………………………………………………….....7
2.3.1 調變介紹……………………………………………………………..8
2.3.2 資料對應方式………………………………………………………..8
2.3.2.1 資料與符元對應……………………………………………...9
2.3.2.2 符元與子碼對應……………………………………………...9
2.3.2.3 訊號符元格式……………………………………………….11
2.3.3 同步標頭格式………………………………………………………12
2.3.4 脈波整形……………………………………………………………12
2.3.5 範例：一個符元……………………………………………………13
2.4 完美接收機………………………………………………………………...16
第三章 偏移振幅調變915 MHz模式之基頻演算法設計………………………..18
3.1 概述 ………………………………………………………………………..18
3.2 通道模型、模擬……………………………………………………………20
3.3 接收端演算法介紹………………………………………………………...21
3.3.1 封包偵測……………………………………………………………22
3.3.2 匹配濾波器…………………………………………………………24
3.3.3 取樣能量偵測與降低取樣頻率……………………………………25
3.3.4 載波頻率偏移估測 (頻率同步) .. …………………………...……25
3.3.4.1 子碼對子碼估測…………………………………………….26
3.3.4.2 符元對符元估測…………………………………………….26
3.3.5 剩餘載波頻率偏移補償………………………………………..…..29
3.3.6 時間同步…………………………………………………………....30
3.3.7 解展頻……………………………………………………………....32
3.3.8 封包偵測誤警的偵錯機制…………………………………………34
3.4 演算法模擬………………………………………………………………...35
第四章 硬體電路架構………………………………………………………………37
4.1 傳送端……………………………………………………………………...37
4.1.1 傳送端量化………………...……………………………………….37
4.1.2 同步標頭與符元子碼對應部分……………………………………39
4.1.3 脈波整型部份…...………………………………………………….40
4.2 接收端……………………………………………………………………...41
4.2.1 接收端量化與效能模擬比較………………………………………42
4.2.2 封包偵測部份………………………………………………………44
4.2.3 載波頻率偏移估測部份……………………………………………45
4.2.4 數位式座標旋轉計算單元…………………………………………46
4.2.5 剩餘載波頻率偏移補償…………………………………………48
4.2.6 時間同步……………………………………………………………50
4.2.7 解展頻………………………………………………………………50
第五章 設計結構及模擬與量測……………………………………………………51
5.1 合成架構、設計考量……………………………………………………….51
5.2 規格表與晶片……………………………………………………………...52
5.3 相關量測結果…………………………………………………………...…54
5.4.1 Pre-Sim………………………………………………………………54
5.4.2 Post-Sim……………………………………………………………..55
第六章 結論與未來展望……………………………………………………………58
中英對照表…………………………………………………………………………..59
全名縮寫對照表……………………………………………………………………..61
參考文獻……………………………………………………………………………..63

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