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研究生:陳智浩
研究生(外文):Chih-Hao Chen
論文名稱:直流偏壓擾動造成功率放大器失真研究與功率結合方式之CMOS推挽式E類功率放大器設計
論文名稱(外文):A Study of Power Amplifier Distortion due to DC Bias Perturbation and a Push-Pull Design of CMOS Class-E Power Amplifier Using Power Combining
指導教授:洪子聖洪子聖引用關係
指導教授(外文):Tzyy-Sheng Horng
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:95
中文關鍵詞:功率放大器功率結合偏壓擾動
外文關鍵詞:Power AmplifierPower CombiningBias perturbation
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中文提要:
本論文探討偏壓擾動形式之記憶效應對數位預失真技術的影響,在輸入不同頻寬之連續波多音訊號及數位調制訊號條件下,討論數位預失真技術之效能。記憶效應會對數位預失真技術造成相當大的影響,而偏壓擾動是記憶效應的重要來源之一。當降低偏壓擾動後,對數位預失真技術的效果會有所改善。本論文另一重點是利用0.18 μm CMOS製程來設計ㄧ個E類功率放大器晶片,設計上利用電晶體疊接架構來減緩崩潰電壓的問題,並且使用功\率結合技術在晶片中完成阻抗轉換,以提高輸出功率與效率。
Abstract:
This thesis studies the memory effect due to bias perturbation on digital predistortion technique, and employs multi-tone continuous wave signal and digital modulation signals with different bandwidth to discuss the performance of digital predistortion technique. Memory effect makes a great impact on the digital predistortion technique, and bias perturbation is one of the major causes. Lowering the bias perturbation can improve the effectiveness of digital predistortion technique. Another focus of this thesis is to design a Class E power amplifier in 0.18 μm CMOS process. The power amplifier uses cascode structure to alleviate the breakdown voltage problem and employs power combining technique to achieve impedance transformation on chip for the purpose of increasing the output power and efficiency.
目錄 I
圖表目錄 III
第一章 序論 1
1.1 背景簡介 1
1.2 文獻探討 2
1.3 章節規劃 3
第二章 功率放大器線性化技術 4
2.1 非線性特性 4
2.1.1 増益壓縮[31] 4
2.1.2 交互調變失真[31] 6
2.1.3 三階交越點[31] 7
2.1.4 多音交互調變比例[1] 8
2.1.5 鄰近通道功率比例[1] 9
2.1.6 雙音與複音交互調變失真之關係[1] 10
2.1.7 放大器的非線性AM/AM和AM/PM轉換特性[1] 11
2.2 功率放大器線性化技術 12
2.2.1 查表式基頻數位預失真器[6] 13
2.2.2 數位預失真電路架構 16
2.3 基頻數位預失真射頻發射機系統量測結果 18
2.3.1 AM/AM 與AM/PM非線性特性之量測結果 19
2.3.2單音訊號測試之量測結果 20
2.3.3雙音訊號測試之量測結果 20
2.3.4十音訊號測試之量測結果 23
2.3.5 QPSK調制訊號測試之量測結果 26
第三章 功率放大器記憶性偏壓擾動效應 31
3.1 記憶效應 31
3.1.1 電路之記憶效應[7] 34
3.1.2 電熱之記憶效應[7] 37
3.1.3 振幅之記憶效應[7] 39
3.2 記憶效應的線性化技術 41
3.2.1 波包濾波技術[7] 41
3.2.2 波包注入技術[7] 43
3.2.3 阻抗最佳化[7] 45
3.3 偏壓擾動對基頻數位預失真技術影響之量測結果 46
3.3.1 雙音訊號測試之量測結果 47
3.3.2 十音訊號測試之量測結果 52
3.3.3 QPSK調制訊號測試之量測結果 56
第四章 CMOS E類功率放大器之設計 63
4.1 架構簡介 64
4.2 設計流程 66
4.3 模擬與量測結果 68
第五章 結論 76
參考文獻 79
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