臺灣博碩士論文加值系統

隨著多媒體需求的日益增加，多核心系統架構常用以並行處理大量資料運算的進行，以往大量資料傳遞是靠著獨立的DMA控制來完成，常會有以下的缺點(1)由於資料傳遞必須透過一讀一寫的方式來完成，造成記憶體訊號取存時脈的負擔，(2)大量的佔用頻寬，造成與處理器在使用Bus上的碰撞。根據以上缺點，本論文整合具DMA功能之記憶體控制器，提出了一個透過AMBA指令的內部快速資料交換機制，藉由DDR2的高時脈傳遞，來實現(1)以記憶體的原有取存時脈進行記憶體之間的傳輸，(2)記憶體對裝置之間的傳輸，可於控制器內部橋接達成。不但可以大幅的降低在System Bus上的工作負擔，並且提供大量資料搬運的目的，縮減傳遞資料所耗費的時間，釋放Bus的使用權給其他周邊裝置，提升整體系統的使用效率，同時也於控制器內實現SATA介面的橋接器，透過DDR2當作資料緩衝的記憶體，增進資料取存的效率並提供強固型資料緩衝機制，可以有效降低固態硬碟的存取次數，延長其工作的壽命。根據模擬結果顯示，傳統DMA傳輸與使用快速資料交換機制相比較，在DDR2最小提供頻寬下，可以節省約51%的傳輸時間，在DDR2可提供之最大頻寬下，可以節省87%的傳輸時間。

With the increasing demand for multi-media,multi-core system architecture used in parallel processing of large amounts of data to carry out operations,in the past,large amounts of data is transferred through an independent control of DMA,and often have the following shortcomings,(1)As a result of the transmission of data is completed by reading and writing,caused the burden of memory clock singnal,(2)A large number of occupied bandwidth,caused the collision with processor by using the data bus. Based on the above shortcomings, this paper proposed an internal fast data switching mechanism through AMBA instruction by integrating the memory controller and DMA function. With the high transmission clock rate of DDR2, to achieve (1) transfer data by the original memory clock rate between memory and memory, (2) transmission between memory and device can be reached by bridge of the controller. Can significantly reduce not only the System Bus in the workload and provide the purpose of handling large amounts of data, to reduce the transmission of data on the amount of time spent and release of the right to use the Bus to other peripheral devices and to enhance the efficiency of the overall system.We also achieved the interface of SATA bridge in the controller. Through the DDR2 memory buffer to enhance the efficiency of accessing information and to provide strong type on the data buffer mechanism, can effectively reduce the number of solid-state hard disk access, the extension of its work life. According to the simulation results show that the use of traditional DMA transfer mechanism for the rapid exchange of data, compared to provide a minimum bandwidth in DDR2, you can save about 51% of transmission time, in the DDR2 maximum bandwidth available, you can save 87% of transmission time.

第一章 緒論 1
1.1 研究動機 1
1.2 研究目的 1
1.3 論文架構 2
第二章 相關研究 3
2-1 DDR2相關研究 3
2-1-1 DRAM & SDRAM 3
2-1-2 DDR & DDR2 4
2-1-3 DDR2規格研究 10
2-1-4 DDR2指令介紹 13
2-1-5 記憶體狀態轉換 16
2-1-6 初始化流程 17
2-1-7 暫存器設定 18
2-1-8 指令時序 20
2-1-9 讀取 & 寫入 20
2-1-10 多資料傳輸 22
2-2 各家廠商控制器介紹 23
2-3 Serial ATA 27
2-3-1 SATA Protocol 27
2-3-2 Primitives介紹 29
2-3-3 Register & Data FIS 31
2-3-4 48bit LBA定址 32
2-3-5 CRC & Scrambler 33
2-3-6 8b/10b 34
第三章 DDR2控制器架構設計 36
3-1 控制器架構設計 36
3-1-1 多核心系統架構 36
3-1-2 控制器架構 37
3-1-3 SATA Bridge 39
3-2 指令設計 41
3-2-1 記憶體定址 41
3-2-2 暫存器設計 43
3-3 Tunnel Mechanism 45
3-3-1快速內部資料交換機制 45
3-3-2 資料轉傳 47
3-3-3 強固型資料緩衝機制 48
第四章 模擬與分析 49
4-1 設計指令測試 50
4-1-1 初始化指令測試 50
4-1-2 單筆寫入與讀取測試 52
4-1-3 多筆寫入與讀取測試 53
4-1-4 DMA指令測試 55
4-1-5 SATA介面指令測試 56
4-2 傳統DMA與資料交換機制效能比較 59
4-3 晶片製作 62
4-3-1 gate-level驗證 63
4-3-2 Post-Simulation驗證 66
4-3-3 Layout 圖 69
4-4 應用之環境 70
4-4-1 Network Routing 70
4-4-2 Reconfigurable FPGA 71
4-4-3 跨控制器之SATA介面與DDR2資料轉傳 72
第五章 結論 73
參考文獻 74

[1]JEDEC DDR2 SDRAM Specification
[2]AMBA Specification (Rev 2.0)
[3]Micron 1Gb SDRAM Data Sheet “MT47H128M8HQ-25”
[4]Micron 1Gb SDRAM Data Sheet “MT47H64M16HR-25”
[5]Transcend JetRAM memory - 2 GB - DIMM 240-pin - DDR2 “JM800QLU-2G”
[6]Micron 512Mb SDRAM Data Sheet “MT47H32M16”
[7]Fu-Min Huang, “An Aggressive Memory controller with Memory Access Scheduling and Bank Precharge Strategies” Dept. Elect. Eng. NCKU, Tainan, Taiwan, ROC. 2004
[8]Ning-Yaun Ker, “A low-Power SDRAM Controller on an 8-bit RISC CPU” Dept. Elect. Eng. NCKU, Tainan, Taiwan, ROC. 2002
[9]Shuang-yan Chen, “An Innovative Design of the DDR/DDR2 SDRAM Compatible Controller” ICASIC.2005
[10]Virtex-4 FPGA Data Sheet
[11]DDR2 SDRAM Controller, Altera corporation.
[12]TI DDR2 SDRAM Controller. Available: http://www.ti.com/
[13]Lattice DDR2 SDRAM Controller. Available: http://www.latticesemi.com
[14]Primecell DDR2 Dynamic Memory Controller. Available: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0418d/index.html
[15]Beyond DDR2/DDR SDRAM Memory Controller. Available : http://www.beyondsemi.com/page/products/interface_cores/beyond_ddr_sdram_memory_controller
[16]DDC DDR/DDR2 Memory Controller. Available: http://www.digidescorp.com/products/IP/DataSheets/DDC_DDR_datasheet.pdf
[17]HyperDrive Multi-port DDR2 Memory Controller IP. Available : http://www.altera.com.cn/products/ip/iup/memory/m-mtx-multiport-hyperdrive-sdram.html
[18]Serial ATA International Organization , Serial ATA Revision2.5. 27 October 2005
[19]“Serial ATA: High Speed Serialized at Attachment Revision 1.0 ” Serial ATA Working Group.
[20]Aloaa R. Fouli, “Serial ATA Host Controller: A Hardware Implementation” The 6th International Workshop on System on Chip for Real Time Applications. IEEE 2006.
[21]Wei Wu, Hai-bing Su, Qin-zhang Wu “A High Performance Serial ATA Host Controller” International Conference on Computer Science and Software Engineering 2008.
[22]A. X. Widmer, P. A. Franaszek, “A DC-Balance, Partitioned-Block, 8B/10B Transmission Code” IBM Journal Research and Development, 1983.
[23]張木吉, “多核心資料交會機制於AMBA之設計,” 碩士論文, 國立中山大學電機工程學系,2008
[24]Cyclone II DSP Development Board Reference Manual “EP2C70F672-C6”
[25]Micron 512Mb SDRAM Simulation Model “MT47H32M16”
[26]Micron 256MB DDR2 SDRAM UDIMM Data Sheet “MT4HTF3264A”