臺灣博碩士論文加值系統

在同步電路設計中，時脈偏移的最小化是非常困難的，因為在單一的時鐘樹下需要滿足多個不同的限制，而限制是發生在複雜的電壓模式環境下，會有特定的模組運作在不同的電壓下。在本篇論文中，我們主要利用可調變延遲緩衝器的，可調變延遲的特性，在不同的電壓模式下，最小化時脈偏移。假設已經擺放固定個數和位置的可調變延遲緩衝器，我們提出了一個線性計算時間最佳化演算法，可以決定每個可調變延遲緩衝器的數值，使得在利用可調變延遲緩衝器做調整下，時脈偏移的結果會最佳化。並且我們提出了一個有效率探索的方法，決定好的位置來擺放這些可調變延遲緩衝器。我們實驗結果顯示出有意義的改進相較於沒使用這些可調變延遲緩衝器。

In synchronous circuit designs, clock skew is difficult to minimize because a single physical layout of a clock tree must satisfy multiple constraints in a complicated power mode environment where certain modules may operate with different voltages. In this paper, we use Adjustable Delay Buffers (ADB) whose delays can be tuned or adjusted to minimize clock skew under different power modes. Assuming that the positions of k ADBs are already determined, we propose a linear-time optimal algorithm which assigns the values of ADBs so that the skew is optimal among all possible ADB assignments. We also propose an efficient heuristic to determine good positions for ADBs. Our results show significant improvement when compared to cases without ADBs.

Abstract 5
List of Contents: 6
List of Figures: 7
List of Tables: 8
Chapter 1 Introduction 9
Chapter 2 Illustrative Example 13
Chapter 3 A Linear Time Optimal Assignment for Adjustable Delay Buffer 15
3.1. Leaf Node Partitioning 17
3.2. Skew-Optimal Linear Time Algorithm 21
3.3. Calculation of Clock Skew under Optimal Assignments 27
3.4. Reduction of The Maximum Clock Latency 29
Chapter 4 Efficient Heuristic for ADB Position Selection 31
4.1 Dealing with Multiple Modes of A Clock Tree 34
Chapter 5 Experimental Results 35
Chapter 6 Conclusions 39
References 41

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