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研究生:翁偲傑
研究生(外文):Weng, Ssu-Chieh
論文名稱:穿隧式低溫多晶矽薄膜電晶體研製與應用
論文名稱(外文):Fabrication and Application of Tunneling Low Temperature Poly-Silicon Thin Film Transistors
指導教授:李敏鴻
指導教授(外文):Lee, Min-Hung
學位類別:碩士
校院名稱:國立臺灣師範大學
系所名稱:光電科技研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:65
中文關鍵詞:次臨界擺幅可靠度穿隧式薄膜電晶體
外文關鍵詞:subthreshold swingReliabilityTunnelingThin Film Transistors
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利用band to band tunneling的觀念,試著驗證可將subthreshold swing小於60 mV/dec.。側向多晶矽的p/i/n結構不只是光二極體,也可以是穿隧式薄膜電晶體在未來的應用上。而我們去驗證水平低溫多晶矽薄膜電晶體並且檢驗元件的可靠度(Reliability)。實驗中得知,穿隧電流隨溫度的變化可以加以證明,確實是band to band tunneling效應的影響;再與一般薄膜電晶體比較可靠度也是相對的好。最後,用垂直式(vertical)不同的結構去驗證是否也有穿隧效應,並且用TCAD-ISE去模擬驗證其結果。 目前為止,穿隧式薄膜電晶體仍有些需要被解決的問題。此論文目的就是透過元件製程與電性分析及元件模擬的各項參數來實踐獲得高效能的穿隧式薄膜電晶體。由於穿隧式薄膜電晶體可如傳統式薄膜電晶體用於邏輯電路上,所以穿隧式薄膜電晶體替代在低功率行動裝置上的應用是一個前瞻性的元件。
The concept of band to band tunneling from p+ and n+ region is researched to realize for Tunneling–TFTs with subthreshold swing < 60 mV/dec. We have demonstrated the LTPS planar Tunneling-TFTs and examined the reliability. The lateral poly-Si p/i/n structure is not only photodiode, but also tunneling-TFTs for future applications. The temperature dependence of tunneling current proves that the current is indeed due to the band to band tunneling effect. The Tunneling-pTFTs exhibits excel threshold voltage stability under constant drain current stress as compare with classical pTFTs for self-heating effect. The practical devices with the gate-controlled tunneling current and the low off-current attracts for the applications in the future. Final, the different structure of vertical is to verify whether the tunnel effect and utilize TCAD-ISE simulation results to verify.
So far, some issues of Tunneling-TFTs are still need to be resolved. In this thesis, further study of various device parameters for obtaining high-performance Tunneling-TFTs is carried out via process and electrical characteristics of device. Since there are not too many additional process steps compare with MOSFET, the Tunneling-TFTs is an advancing device for low-power mobile applications.
Publication Ⅰ
中文摘要 Ⅱ
Abstract Ⅲ
致謝 Ⅳ
目錄 Ⅴ
第一章 簡介 p.1
1-1 穿隧式薄膜電晶體的背景與動機 p.1
1-2 論文架構 p.8
第二章 原理 p.11
2-1 PN二極體、P-I-N二極體與Esaki穿隧二極體 p.11
2-1-1 PN二極體 p.11
2-1-2 P-I-N二極體 p.12
2-1-3 Esaki穿隧二極體 p.14
2-2 穿隧式薄膜電晶體操作原理與定義 p.18
2-3 熱載子效應及自我加熱效應 p.20
2-3-1 熱載子效應(hot-carrier) p.20
2-3-2 自我加熱效應(self-heating) p.25
第三章 穿隧式與一般薄膜電晶體的穩定度分析比較 p.27
3-1 水平穿隧式薄膜電晶體製作流程 p.28
3-2 電穩定性結果與討論 p.33
3-2-1 電性量測儀器設定 p.33
3-2-2 偏流(current bias stress)電穩定性與一般薄膜電晶體比較 p.36
第四章 垂直穿隧式薄膜電晶體製作與特性 p.44
4-1 垂直穿隧式薄膜電晶體製作流程 p.45
4-2 電性結果與討論 p.51
第五章 結論與未來待續研究 p.60
參考文獻 p.63
[1] F. Mayer, C. Le Royer, J.-F. Damlencourt, K. Romanjek, F. Andrieu, C. Tabone, B. Previtali, and S. Deleonibus, “Impact of SOI, Si1-XGeXOI and GeOI substrates on CMOS compatible Tunnel FET performance, ” in IEDM Tech. Dig., pp. 163-166, 2008.
[2] T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, “Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With Record High Drive Currents and <60mV/dec Subthreshold Slope, ” in IEDM Tech. Dig., pp. 947-949, 2008.
[3] E. Takeda, H. Matsuoka, Y. Jgura, and S. Asai, “A Band to band Tunneling MOS Device (B2T-MOSFET) --- A Kind of “Si Quantum Device” ---, ” in IEDM Tech. Dig., pp. 402-405, 1988.
[4] M. Takayanagi, S. Iwabuchi, T. Kobori, and T. Wada, “A New Band-to-Band Tunneling Model for Accurate Device Simulation of Si MOSFETs, ” in IEDM Tech. Dig., pp. 311-314, 1989.
[5] K. K. Bhuwalka, J. Schulze, and I. Eisele, “Performance Enhancement of Vertical Tunneling Field-Effect Transistor with SiGe in the δp+ Layer, ” Jap. J. of Appl. Phy., vol. 43, no. 7A, pp. 4073-4078, 2004.
[6] M Sterkel, P-FWang, T Nirschl, B Fabel, K K Bhuwalka, J Schulze, I Eisele, D Schmitt-Landsiede ,and W Hansch, “Characteristics and Optimization of Vertical and Planar Tunneling-FETs, ” Journal of Physics: Conference Series 10, pp. 15–18, 2005.
[7] S. Salahuddin, and S. Datta, “Can the subthreshold swing in a classical FET be lowered below 60 mV/decade?, ” in IEDM Tech. Dig., pp. 693-696, 2008.
[8] M. H. Lee, P. S. Chen, W.-C. Hua , and C.-Y. Yu, ” Comprehensive Low-Frequency and RF Noise Characteristics in Strained-Si NMOSFETs , ” in IEEE IEDM Tech. Dig. , PP. 69-72, 2003.
[9] M. H. Lee, K.-Y. Ho, P.-C. Chen, C.-C. Cheng, S. T. Chang, M. Tang, M. H. Liao, and Y.-H. Yeh, “Promising a-Si:H TFTs with High Mechanical Reliability for Flexible Display, ” in IEEE IEDM Tech. Dig. , PP. 299-302, 2006.
[10] Mutsumi Kimura, Takehiro Shima, Takehiko Yamashita, Yoshitaka Nishizaki, Hiroyuki Hara, and Satoshi Inoue, “Artificial Retina using Poly-Si Thin-Film Photodevice and Poly-Si Thin-Film Transistor, “ IDMC, pp. 191-194, 2007.
[11] S. M. Sze, Physics of semiconductor devices, 2nd edition, John Wiley & Sons, Inc., 1981.
[12] P.-F. Wang, “Complementary Tunneling-FETs (CTFET) in CMOS Technology,” Technische Universität München Lehrstuhl für Technische Elektronik Fachgebiet Halbleiterproduktionstechnik, 2003.
[13] Y. Taur, C. H. Wann and D. J. Frank, “25nm CMOS Design Considerations,” in IEEE IEDM Tech. Dig., pp. 789-792 (1998).
[14] K.-H. Lee, S.-C.Wang, and Y.-C. King, “Self-convergent scheme for logic-process-based multilevel/analog memory,” IEEE Transactions on Electron Devices, vol. 52, no. 12, pp. 2676–2681, 2005.
[15] T.-C. Ong, P.-K. Ko, and C. Hu, “Hot-carrier current modeling and device degradation in surface-channel p-mosfet’s,” IEEE Transactions on Electron Devices, vol. 37, no. 7, pp. 1658–1666, 1990.
[16] T. Motai, J. Tsutsumi, K. Nakamura, M. Yoshida, “Analysis on Temperature Dependent Poly-Si TFT Characteristics and Circuit Performances,” Int’l. Workshop on AM-LCD, pp. 271-274, 1999.
[17] 陳志強,“LTPS 低溫多晶矽顯示器技術”,全華科技圖書出版。
[18] S. Inoue, H. Ohshima and T. Shimoda, “Analysis of Degradation Phenomenon Caused by Self-Heating in Low-Temperature-Processed Polycrystalline Silicon Thin Film Transistors,” Japanese Journal of Applied Physics. vol. 41, no. 11A, pp. 6313-6319, 2002.
[19] Y. H. Tai, S. C. Huang, C. W. Lin and H. L. Chiu, “Degradation of the Capacitance-Voltage Behaviors of the Low-Temperature Polysilicon TFTs under DC stress,” Journal of The Electronchemical Society, 154(7) H611-H618, 2007.
[20] H. S. Momose, S. Nakamura, T. Ohguro, T.Yoshitomi, E. Morifuji, T. Morimoto, Y. Katsumata, and H. Iwai, “A study of hot-carrier degradation in n- and p-mosfets with ultra-thin gate oxides in the direct-tunneling regime,” IEDM Tech. Dig., pp.453-456, 1997.
[21] A. T. Voutsas, “Advances in laser annealing technology for poly-Si material engineering and ultra-high-performance device fabrication,” 10th IEEE International Conference on Advanced Thermal Processing of Semiconductors – RTP, pp. 183-191, 2002.
[22] S. Brad Herne, et al., US. Patent No: 7,285,464, 2007.
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