本篇論文中，我們將快取記憶體過濾器的概念應用到處理器中分支預測器(Branch Predictor)之分支目標緩衝器(Branch Target Buffer)設計。使用過濾器概念可以減少分支目標緩衝器的存取動作以降低動態耗電，本篇論文提出分支目標緩衝器的設計方法，不僅可以維持分支預測的準確度與處理器管線架構高效能運作，並且達到省電的效果。
我們使用內容可定址記憶體(CAM)來設計過濾器，並且使用HSPICE、CACTI等工具來確認過濾器電路不影響處理器管線中指令擷取部分之關鍵電路延遲。根據SimpleScalar/Wattch與SPEC2K等工具為基礎的實驗結果顯示，在不犧牲分支預測準確度與處理器效能的前提下，分支目標緩衝器動作減少達到85%，分支預測單元省電達16% - 55%，分支目標緩衝器省電達18% - 75%。

In this paper we apply Sentry Tag based filter scheme to the design of branch target buffer (BTB) of branch predictor in modern processors. The filter scheme filtrates unnecessary accesses of branch target buffer to reduce dynamic power consumption. The proposed scheme not only maintains high branch prediction accuracy and thus high pipeline utilization for processors, but also attains considerable power saving.
We use Content-Addressable Memory (CAM) to design the filter scheme and utilize HSPICE and CACTI tools to make sure the proposed scheme’s critical path delay of processor instruction fetch of pipeline is not affected. Based on SimpleScalar/Wattch simulators and SPEC2K benchmarks, we show that our scheme can filter up to 85% of branch target buffer accesses, thus reducing the power consumption for branch prediction unit by 16% - 55%, (the power consumption for branch target buffer by 18% - 75%) without compromising prediction accuracy and processor performance.

摘要 I
Abstract II
致謝 III
目錄 IV
圖目錄 VI
表目錄 X
第一章 緒論 1
1.1研究動機與目的 1
1.2研究貢獻 3
1.3論文內容簡述 4
第二章 相關背景知識與文獻探討 5
2.1分支預測單元(Branch Prediction Unit) 5
2.1.1分支預測器(Branch Predictor) 7
2.1.2分支目標緩衝器(Branch Target Buffer) 20
2. 相關文獻 22
2.2.1 NBIC低耗電分支目標緩衝器 22
2.2.2 NBDT低耗電分支目標緩衝器 24
2.2.3 PPD低耗電分支目標緩衝器 25
第三章 過濾器方法 27
3.1傳統四路集合關聯式分支目標緩衝器 27
3.2過濾器方法使用在分支目標緩衝器的原理 29
3.3過濾率與平均存取動作的分析 30
3.3.1平均存取動作的分析 31
3.3.2過濾率的分析 33
3.4過濾器方法硬體電路設計 35
第四章 模擬實驗結果與討論 37
4.1對最長路徑的影響 40
4.2哨兵表額外面積 46
4.3哨兵表過濾效能 48
4.4功率節省效果 51
第五章 結論與未來研究方向 61
參考文獻 62

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